Patents by Inventor Assaf Ganor

Assaf Ganor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088459
    Abstract: A coin cell powered device that includes a unit and one or more interfaces that are configured to interface between the unit, the cell coin and an external capacitor. The unit may include a regulator, a transmitter and a charge pump. The transmitter is configured to transmit signals during a transmission period while receiving power from the regulator, the power originated from the external capacitor. The charge pump is configured to perform, during a charging period, a charging process for charging the external capacitor to a charged voltage that exceeds a voltage of the cell coin, wherein the charging process may include iterations of (a) charging a charge pump capacitor by the coin cell, and (b) discharging the charge pump capacitor thereby charging the external capacitor. The capacitance of the charge pump capacitor is a fraction of a capacitance of the external capacitor. The duration of the charging period exceeds a duration of the transmission period.
    Type: Application
    Filed: September 22, 2023
    Publication date: March 14, 2024
    Inventors: Assaf Ganor, Tzahi Shalit, Levi Schultz
  • Patent number: 11811026
    Abstract: A coin cell powered device includes a regulator, a transmitter and a charge pump. The transmitter is configured to transmit signals during a transmission period while receiving power from the regulator, the power originated from an external capacitor. The charge pump is configured to perform, during a charging period, a charging process for charging the external capacitor to a charged voltage that exceeds a voltage of a cell coin, wherein the charging process may include iterations of (a) charging a charge pump capacitor by the coin cell, and (b) discharging the charge pump capacitor thereby charging the external capacitor. The capacitance of the charge pump capacitor is a fraction of a capacitance of the external capacitor. The duration of the charging period exceeds a duration of the transmission period.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: November 7, 2023
    Assignee: DSP Group Ltd.
    Inventors: Assaf Ganor, Tzahi Shalit, Levi Schultz
  • Patent number: 11222654
    Abstract: A method for voice detection, the method may include (a) generating an in-ear signal that represents a signal sensed by an in-ear microphone and fed to a feedback active noise cancellation (ANC) circuit; (b) generating at least one additional signal, based on at least one out of a playback signal and a pickup signal sensed by a voice pickup microphone; and (c) generating a voice indicator based on the in-ear signal and the at least one additional signal.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 11, 2022
    Assignee: DSP GROUP LTD.
    Inventors: Assaf Ganor, Ori Elyada
  • Patent number: 11163531
    Abstract: A method and a MAC unit that may include accumulation unit and a multiplier. A accumulation unit that includes a first part, a second part and a third part. The first part may calculate a truncated sum. The second part may be configured to (a) receive, during each calculation cycle, a carry out of an add operation performed during a calculation cycle, (b) receive a sign bit of an intermediate product calculated during the calculation cycle; and (c) calculate, by the counter logic, a counter logic value, and (d) convert, after a start of a last calculation cycle of the calculation cycles, an output value of the counter logic to an intermediate value having a two's complement format. The third part may be configured to calculate an output value of the MAC unit based on the intermediate value and a truncated sum calculated by the first part of the accumulation unit.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: November 2, 2021
    Assignee: DSP GROUP LTD.
    Inventors: Moshe Haiut, Assaf Ganor
  • Publication number: 20200313246
    Abstract: A coin cell powered device that includes a unit and one or more interfaces that are configured to interface between the unit, the cell coin and an external capacitor. The unit may include a regulator, a transmitter and a charge pump. The transmitter is configured to transmit signals during a transmission period while receiving power from the regulator, the power originated from the external capacitor. The charge pump is configured to perform, during a charging period, a charging process for charging the external capacitor to a charged voltage that exceeds a voltage of the cell coin, wherein the charging process may include iterations of (a) charging a charge pump capacitor by the coin cell, and (b) discharging the charge pump capacitor thereby charging the external capacitor. The capacitance of the charge pump capacitor is a fraction of a capacitance of the external capacitor. The duration of the charging period exceeds a duration of the transmission period.
    Type: Application
    Filed: March 4, 2020
    Publication date: October 1, 2020
    Applicant: DSP Group Ltd.
    Inventors: Assaf Ganor, Tzahi Shalit, Levi Schultz
  • Publication number: 20200273486
    Abstract: A method for voice detection, the method may include (a) generating an in-ear signal that represents a signal sensed by an in-ear microphone and fed to a feedback active noise cancellation (ANC) circuit; (b) generating at least one additional signal, based on at least one out of a playback signal and a pickup signal sensed by a voice pickup microphone; and (c) generating a voice indicator based on the in-ear signal and the at least one additional signal.
    Type: Application
    Filed: January 13, 2020
    Publication date: August 27, 2020
    Applicant: DSP Group Ltd.
    Inventors: Assaf Ganor, Ori Elyada
  • Publication number: 20200034117
    Abstract: A method and a MAC unit that may include accumulation unit and a multiplier. A accumulation unit that includes a first part, a second part and a third part. The first part may calculate a truncated sum. The second part may be configured to (a) receive, during each calculation cycle, a carry out of an add operation performed during a calculation cycle, (b) receive a sign bit of an intermediate product calculated during the calculation cycle; and (c) calculate, by the counter logic, a counter logic value, and (d) convert, after a start of a last calculation cycle of the calculation cycles, an output value of the counter logic to an intermediate value having a two's complement format. The third part may be configured to calculate an output value of the MAC unit based on the intermediate value and a truncated sum calculated by the first part of the accumulation unit.
    Type: Application
    Filed: June 21, 2019
    Publication date: January 30, 2020
    Inventors: MOSHE HAIUT, Assaf Ganor
  • Patent number: 10228755
    Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel Corporation
    Inventors: Doron Rajwan, Efraim Rotem, Avinash N. Ananthakrishnan, Ankush Varma, Assaf Ganor, Nir Rosenzweig, David M. Pawlowski, Arik Gihon, Nadav Shulman
  • Patent number: 10001822
    Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: June 19, 2018
    Assignee: Intel Corporation
    Inventors: Assaf Ganor, Efraim Rotem, Noam Winer, Omer Vikinski
  • Publication number: 20180095520
    Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: DORON RAJWAN, EFRAIM ROTEM, AVINASH N. ANANTHAKRISHNAN, ANKUSH VARMA, ASSAF GANOR, NIR ROSENZWEIG, DAVID M. PAWLOWSKI, ARIK GIHON, NADAV SHULMAN
  • Patent number: 9673820
    Abstract: A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: June 6, 2017
    Assignee: DSP GROUP LTD.
    Inventor: Assaf Ganor
  • Patent number: 9653989
    Abstract: A system that may include a first direct current to direct current (DC) converter that is arranged to determine at a first determination rate whether to alter a parameter of operation of the first DC to DC converter and to selectively alter the parameter of operation of operation of the first DC to DC converter in response to the determination; and a second switched-mode DC to DC converter that is arranged to determine at a second determination rate whether to alter the parameter of operation of the second DC to DC converter and to selectively alter the parameter of operation of operation of the second DC to DC converter in response to the determination. The second determination rate is higher by at least a factor of two than the first determination rate. The first and second DC to DC converters are mutually unsynchronized.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: May 16, 2017
    Assignee: DSP GROUP Ltd.
    Inventor: Assaf Ganor
  • Publication number: 20170083067
    Abstract: In one embodiment, a processor includes: a power switcher circuit to receive a first voltage and charge at least one charge storage device with the first voltage in a first phase and output charge in a second phase; a selection circuit coupled to the power switcher circuit to couple the output charge to a selected one of a plurality of load circuits responsive to a control signal; and a control circuit to generate the control signal based at least in part on a comparison of a feedback voltage of a rail coupled to the selected load circuit to a reference voltage. Other embodiments are described and claimed.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 23, 2017
    Inventors: Assaf Ganor, Efraim Rotem, Noam Winer, Omer Vikinski
  • Patent number: 9209783
    Abstract: A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: December 8, 2015
    Assignee: DSP GROUP LTD.
    Inventors: Yosef Bendel, Eyal Rosin, Assaf Ganor
  • Publication number: 20150333739
    Abstract: A scheme is described that provides for a low latency, glitch free chip interface that does not require a clock. This invention handles input transitions that are skewed and also input transitions that are momentary. A change in an input state initiates a pulse that propagates through the system and samples the new input state after a delay. If there is a difference between the sampled input state and the present input state, then a new pulse is initiated in order to avoid any illegal transitions at the output.
    Type: Application
    Filed: April 28, 2015
    Publication date: November 19, 2015
    Inventor: Assaf Ganor
  • Publication number: 20150244349
    Abstract: A device, comprising a first interpolator that is configured to (a) receive, at a first clock rate, a first signal having a first sampling rate and (b) output, at a second clock rate, a second signal having a first desired sampling rate average; wherein the first interpolator comprises: a first buffer for storing the first signal; and a first fractional sampling ratio circuit that is configured to generate a first pattern of fixed point values, wherein an average value of the first pattern corresponds to a first desired sampling rate ratio between the first desired sampling rate average and the first sampling rate.
    Type: Application
    Filed: February 4, 2015
    Publication date: August 27, 2015
    Inventors: Yosef Bendel, Eyal Rosin, Assaf Ganor
  • Publication number: 20140035366
    Abstract: A system that may include a first direct current to direct current (DC) converter that is arranged to determine at a first determination rate whether to alter a parameter of operation of the first DC to DC converter and to selectively alter the parameter of operation of operation of the first DC to DC converter in response to the determination; and a second switched-mode DC to DC converter that is arranged to determine at a second determination rate whether to alter the parameter of operation of the second DC to DC converter and to selectively alter the parameter of operation of operation of the second DC to DC converter in response to the determination. The second determination rate is higher by at least a factor of two than the first determination rate. The first and second DC to DC converters are mutually unsynchronized.
    Type: Application
    Filed: August 1, 2013
    Publication date: February 6, 2014
    Inventor: Assaf Ganor