Abstract: An apparatus and method for converting a dual-rail input. The apparatus combines two useful operand bits and two auxiliary operand bits so that, in a data mode, two output operands of three output operands have a value which is different from that of the third output operand. In a preparation mode, the three output operands of the apparatus have the same value. The apparatus and method may preferably be employed in a three-operands adder as an interface between a dual-rail three-bits half adder and a sum-carry stage of a two-bits full adder so to achieve the same level of security as a full implementation of the three-operands adder in dual-rail technology, despite the two-bits full adder being implemented in single-rail technology.

Abstract: A multiplicand is multiplied by a multiplier using a modulus. The multiplicand, the multiplier and the modulus are polynomials of variable. A multiplication look-ahead method to obtain a multiplication shift value is carried out. An intermediate result polynomial is shifted to the left by the number of digits of the multiplication shift value. A reduction shift value equalling the difference of the degree of the shifted intermediate result polynomial and the degree of the modulus polynomial is obtained in a reduction look-ahead method. The modulus polynomial is then shifted by a number of digits equalling the reduction shift value. In a three-operands addition, the shifted polynomial and the multiplicand are summed and the shifted modulus polynomial is subtracted. The modular multiplication are iteratively executed and processed progressively until all the powers of the multiplier polynomial have been processed.

Abstract: A processor includes a source register having a source register content, a destination register, a calculating unit for performing a calculation using the source register content, wherein the calculation is performed in several calculation cycles, and wherein in each cycle only one portion of the source register content is useable, a data bus connected to the source register, the destination register and the calculating unit, and a processor controller. The processor controller is operable to supply the source register content in portions to the calculating unit on the one hand and to the destination register on the other hand during the calculation via the data bus, so that after an execution of the calculation the source register content is written into the destination register. Therefore it is possible to obtain a register copy of a source register the destination register via a limited data bus without additional machine cycles for long operands to be processed in portions.

Abstract: Data processing circuit including a single rail bus having a single rail line, a dual rail bus having a first dual rail line for data bits and a second dual rail line for inverted data bits, and a converter for converting signals on the single rail bus into signals on the dual rail bus and vice versa. The converter has a read driver for transferring signals on the first dual rail line to the single rail bus when the read driver is active, a write driver for transferring the signals on the single rail bus to the first dual rail line when the write driver is active, a producer for producing the signals on the second dual rail line from the signals on the first dual rail line when the write driver is active, and a controller for controlling the drivers so that at most only one driver is active.

Abstract: A calculating unit includes a first calculating unit block, a second calculating unit block, controller, and connector having connecting lines, wherein for each elementary cell having a same significance in the first calculating unit block and the second calculating unit block an individual connecting line is provided to achieve a quick register exchange by means of the controller of the calculating unit blocks operating in parallel.

Abstract: Calculating unit having adder blocks, each having single adders, a carry input, a carry output, and a carry pass output, wherein a signal at the carry pass output is indicative of a carry passing through the adder block. Depending on the carry pass output signal, a clock generator for feeding the adder blocks with operands to be processed is decelerated. A determining unit determines in which of the adder blocks a least significant bit of an operand to be subtracted is disposed. A deactivating unit deactivates a carry pass output of adder block(s) provided for lower order digits with respect to the adder block in which the least significant bit is disposed, and a feeding unit feeds a carry into the carry input of this adder block in which the least significant bit is disposed.

Abstract: A calculating unit comprises several adder blocks with single adders, a clock generator and control means. A carry pass means is associated with each adder block, which determines whether a carry passes fully through the respective adder block. If it is determined that the carry does not pass through any of the adder blocks, the calculating unit is clocked with a clock period, which is sufficient that the carry passes almost fully through an adder block, and passes through at least part of the upstream adder block. If it is determined, that the carry passes fully through an adder block, a panic signal is generated. The adder block is decelerated, so that the clock period is high enough that the carry additionally fully passes through another adder block. Only in a case of panic signals of two adjacent adder blocks, is the calculating unit is decreased so much, that the carry passes from the least significant digit of the calculating unit to the most significant digit of the calculating unit.

Abstract: A register cell includes a first input for a data unit to be written into the register cell. The register cell includes further a second input for a negated data unit to be written into the register cell. A first pair of oppositely coupled inverters as a first storage circuit is adapted to be coupled to the first input. A second pair of oppositely coupled inverters as a second storage circuit is adapted to be coupled to a second input. Using two oppositely coupled pairs of inverters makes it possible to initialize both the first input and the second input of the register either to a high voltage state (precharge) or to a low voltage state (discharge), such that the power consumption of the register cell is homogenized from one working clock to the next.

Abstract: In a method for modular multiplication using a multiplication look-ahead process for computing a multiplication shift value and a reduction look-ahead process for computing a reduction shift value, a modulus is first transformed into a transformed modulus that is greater than said modulus. The transformation is carried out such that a predetermined fraction of the transformed modulus has a higher-order digit with a first predetermined value that is followed by at least one low-order digit having a second predetermined value. During the iterative working off of the modular multiplication using the multiplication look-ahead process and the reduction look-ahead process, the transformed modulus is utilized so as to obtain at the end of the iteration a transformed result for the modular multiplication. Finally, the transformed result is re-transformed by modular reduction using the original modulus.

Abstract: In a method for modular multiplication of a multiplicand by a multiplier using a modulus, 1 multiplication shift values are initially determined by means of a multiplication-lookahead method while taking into account 1 blocks of consecutive digits of the multiplier. Subsequently, 1 reduction shift values are determined by means of a reduction-lookahead method for the 1 blocks of digits of the multiplier. The 1 multiplication shift values and the 1 reduction shift values are applied to an intermediate result from a previous iteration step, to the modulus or to a value derived from the modulus, and to the multiplicand, so as to obtain the 21+1 operands. By means of a multi-operands adder, the 21+1 operands are combined to obtain an updated intermediate result for an iteration step following the previous iteration step, the iteration being continued for such time until all digits of the multiplier have been processed.

Abstract: A processor comprises an arithmetic unit for processing operands, a register memory for storing operands with a register memory space and a register memory configuration unit. The register memory configuration unit is designed to configure the register memory such that memory space in the register memory is assigned to operands, and that memory space in the register memory that is not assigned to operands will be made available for other data than the operands. Thereby, on the one hand the number of operand transfers between an external bus and the arithmetic unit is decreased, since as many operands as possible are stored in the register memory, while on the other hand, when part of the register memory is not needed for storage of operands, this part will not be idle but made available for other data, so that the memory resources of the processors are always utilized optimally.

Abstract: An inventive electronic circuit includes central processing means having a clock connection and a data connection, as well as a peripheral unit having a clock connection and a data connection, the clock connection of the peripheral unit being connected to a signal output of a controllable oscillator or to an external clock input. Synchronization means having a first and a second data connection is connected, the first data connection being connected to the data connection of the peripheral unit. In addition a data bus connects the data connection of the CPU and the second data connection of the synchronization means. The clocking of the peripheral unit asynchronous to the central processing unit yields a more effective operation being better adjustable to certain parameters, such as, for example, the application and the energy of the electronic circuit available.

Abstract: An inventive electronic circuit includes a controller for processing a processor task as well as an energy determination means for determining the energy available to the controller. A control means of the electronic circuit controls the controller depending on the energy available to the controller. An optimum utilization of the energy available and, thus, an optimization of the computing speed with maximum energy utilization is achieved by means of the energy control.

Abstract: A cryptography processor includes a central processing unit and a co-processor, the co-processor comprising a plurality of calculating subunits as well as a single control unit which is coupled to each of the plurality of calculating subunits. A cryptographic operation is distributed among the individual calculating subunits in the form of sub-operations by the control unit. The central processing unit, the plurality of calculating subunits and the control unit are integrated on a single chip, the chip comprising a common supply current access for supplying the plurality of calculating subunits and the control unit with current. Due to the arrangement of the calculating subunit in parallel, on the hand, the throughput of the cryptography processor is increased. On the other hand, however, the current profile that may be detected at the supply current access is randomised to such an extent that an attacker can no longer infer numbers processed in the individual calculating subunits.

Abstract: A cryptographic processor for performing operations for cryptographic applications comprises a plurality of coprocessors, each coprocessor having a control unit and an arithmetic unit, a central processing unit for controlling said plurality of coprocessors and a bus for connecting each coprocessor to the central processing unit. The central processing unit, the plurality of coprocessors and the bus are integrated an one single chip. The chip further comprises a common power supply terminal for feeding said plurality of coprocessors. By way of parallel connection of various coprocessors, there is obtained an the one hand an increase in throughput and an the other hand an improvement in security of the cryptographic processor with respect to attacks that are based an the evaluation of power profiles of the cryptographic processor, since power profiles of a least two coprocessors are superimposed.

Abstract: In a method for modular multiplying a multiplicand by a multiplier using a modulus, the multiplicand, the multiplier and the modulus being polynomials of variable, a multiplication look-ahead method to obtain a multiplication shift value is carried out. An intermediate result polynomial is shifted to the left by the number of digits of the multiplication shift value to obtain a shifted intermediate result polynomial. Furthermore, a reduction look-ahead method to obtain a reduction shift value is carried out, the reduction shift value equalling the difference of the degree of the shifted intermediate result polynomial and the degree of the modulus polynomial. The modulus polynomial is then shifted by a number of digits equalling the reduction shift value to obtain a shifted modulus polynomial. In a three-operands addition, the shifted intermediate result polynomial and the multiplicand are summed and the shifted modulus polynomial is subtracted to obtain an updated intermediate result polynomial.