Patents by Inventor Asuka Nomura

Asuka Nomura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11939459
    Abstract: An object of the present invention is to provide a photosensitive resin composition having good liquid repellency. The photosensitive resin composition of the present invention at least contains a fluororesin having a crosslinking site, a solvent, and a photopolymerization initiator, and the fluororesin contains a repeating unit derived from a hydrocarbon having a fluorine atom.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: March 26, 2024
    Assignee: Central Glass Company, Limited
    Inventors: Yuzuru Kaneko, Satoru Miyazawa, Keiko Sasaki, Asuka Sano, Yusuke Nomura
  • Patent number: 7279386
    Abstract: A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: October 9, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mark C. Kelling, Douglas Bonser, Srikanteswara Dakshina-Murthy, Asuka Nomura
  • Patent number: 7223698
    Abstract: A method of forming a shallow trench isolation (STI) region in a silicon substrate creates an STI region that extends above a top surface of the silicon substrate. A planarizing dielectric layer is formed on the substrate and extends above the field oxide regions. The planarizing dielectric layer is removed by chemical mechanical polishing or blanket etch back, for example, as well as those portions of the field oxide regions that extend above the top surface of the substrate and the active regions. The step height is thereby eliminated or significantly reduced.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: May 29, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas J. Bonser, Srikanteswara Dakshina-Murthy, Mark C. Kelling, John G. Pellerin, Johannes F. Groschopf, Edward Asuka Nomura
  • Patent number: 7144785
    Abstract: A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.
    Type: Grant
    Filed: November 1, 2004
    Date of Patent: December 5, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Srikanteswara Dakshina-Murthy, Douglas Bonser, Mark C. Kelling, Asuka Nomura
  • Publication number: 20060121711
    Abstract: A method for forming spacers of specific dimensions on a polysilicon gate electrode protects the sidewalls of the polysilicon gate electrode during selective epitaxial growth. The spacers, whether asymmetric or symmetric, are precisely defined by using the same specific exposure tool, such as a 193 nm wavelength step and scan exposure tool, and the same pattern reticle, in both the defining of the polysilicon gate electrode pattern and the pattern spacer, while employing tight alignment specifications.
    Type: Application
    Filed: December 3, 2004
    Publication date: June 8, 2006
    Inventors: Mark Kelling, Douglas Bonser, Srikanteswara Dakshina-Murthy, Asuka Nomura
  • Publication number: 20060094205
    Abstract: A strained silicon semiconductor arrangement with a shallow trench isolation (STI) structure has a strained silicon (Si) layer formed on a silicon germanium (SiGe) layer. A trench extends through the Si layer into the SiGe layer, and sidewall spacers are employed that cover the entirety of the sidewalls within the trench in the SiGe layer. Following STI fill, polish and nitride stripping process steps, further processing can be performed without concern of the SiGe layer being exposed to a silicide formation process.
    Type: Application
    Filed: November 1, 2004
    Publication date: May 4, 2006
    Inventors: Srikanteswara Dakshina-Murthy, Douglas Bonser, Mark Kelling, Asuka Nomura