Abstract: Disclosed are medical devices for sensing bioelectrical potential including an electroencephalography (EEG) headset, electrodes compatible therewith, and methods of operation thereof. The headset can comprise a left junction and a right junction, a plurality of length-adjustable bands connecting the left junction and the right junction, and a number of electrodes. Each of the electrodes can comprise an electrode body coupled to one of the plurality of length-adjustable bands and a detachable electrode tip configured to be detachably coupled to the electrode body. The electrode tip can comprise an electrode tip body, one or more deflectable electrode legs coupled to the electrode tip body, and a conductive cushioning material coupled to a segment of at least one of the one or more electrode legs. The conductive cushioning material can retain or be saturated with one or more conductors.

Abstract: Disclosed are medical devices for sensing bioelectrical potential including an electroencephalography (EEG) headset, electrodes compatible therewith, and methods of operation thereof. The headset can comprise a left junction and a right junction, a plurality of length-adjustable bands connecting the left junction and the right junction, and a number of electrodes. Each of the electrodes can comprise an electrode body coupled to one of the plurality of length-adjustable bands and a detachable electrode tip configured to be detachably coupled to the electrode body. The electrode tip can comprise an electrode tip body, one or more deflectable electrode legs coupled to the electrode tip body, and a conductive cushioning material coupled to a segment of at least one of the one or more electrode legs. The conductive cushioning material can retain or be saturated with one or more conductors.

Abstract: Disclosed are medical devices for sensing bioelectrical potential including an electroencephalography (EEG) headset, electrodes compatible therewith, and methods of operation thereof. The headset can comprise a left junction and a right junction, a plurality of length-adjustable bands connecting the left junction and the right junction, and a number of electrodes. Each of the electrodes can comprise an electrode body coupled to one of the plurality of length-adjustable bands and a detachable electrode tip configured to be detachably coupled to the electrode body. The electrode tip can comprise an electrode tip body, one or more deflectable electrode legs coupled to the electrode tip body, and a conductive cushioning material coupled to a segment of at least one of the one or more electrode legs. The conductive cushioning material can retain or be saturated with one or more conductors.

Abstract: A method, computer program storage device and system are provided for determination and selection of optimized circuit components. The method includes performing a timing analysis on at least a portion of an electronic circuit and determining a path in the at least a portion of an electronic circuit, where the path comprises at least one storage element and an operational attribute associated with the path. The method also includes determining an optimized storage element adapted to utilize the operational attribute. The system includes a processing device and at least one of a synthesis tool, a timing tool or a place and route tool communicatively connected to the processing device. The synthesis tool, the timing tool and the place and route tool are adapted to process or analyze an electrical circuit.

Abstract: A method, electronic device, and system are provided in which data is stored in a gateable retention storage element. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus which includes a silicon chip. The method includes storing a data value in a storage element, wherein the storage element is at least one of a flip-flop, a latch or a register. The method also includes placing the storage element in a low power state comprising removing one or more existing connections between the actual ground node and at least one other component in the storage element. The method also includes maintaining the data value in the storage element subsequent to placing the storage element into the low power state. The electronic device includes a storage component for storing a data value.

Abstract: A method, computer program storage device and system are provided for determination and selection of optimized circuit components. The method includes performing a timing analysis on at least a portion of an electronic circuit and determining a path in the at least a portion of an electronic circuit, where the path comprises at least one storage element and an operational attribute associated with the path. The method also includes determining an optimized storage element adapted to utilize the operational attribute. The system includes a processing device and at least one of a synthesis tool, a timing tool or a place and route tool communicatively connected to the processing device. The synthesis tool, the timing tool and the place and route tool are adapted to process or analyze an electrical circuit.

Abstract: Various methods are provided for leakage reduction via optimized reset states and improving performance for storage elements. The methods include selecting a storage element, where the storage element comprises at least one storage element component sized to reduce static current leakage or at least one storage element component adapted to increase at least one of speed or performance of the storage element. The methods also call for determining a preferred reset state for the storage element, wherein the preferred reset state is based at least upon the reduction of static current leakage, the speed or the performance of the storage element. The methods also call for setting the storage element reset state to the preferred reset state.

Abstract: A method, electronic device, and system are provided in which data is stored in a gateable retention storage element. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create an apparatus which includes a silicon chip. The method includes storing a data value in a storage element, wherein the storage element is at least one of a flip-flop, a latch or a register. The method also includes placing the storage element in a low power state comprising removing one or more existing connections between the actual ground node and at least one other component in the storage element. The method also includes maintaining the data value in the storage element subsequent to placing the storage element into the low power state. The electronic device includes a storage component for storing a data value.

Abstract: A scannable flop circuit configured for operation in a multiple modes. The scannable flop circuit includes a functional flop having a data input, a clock input, and a data output, a scan flop having a scan data input and a scan data output, and a latch circuit coupled between the functional flop and the scan flop. The latch circuit includes one or more mode signal inputs to enable selection of an operating mode. In a first mode, the latch circuit is configured to enable the functional flop to provide a data signal to the scan flop. In a second mode, the latch circuit is configured to enable the scan flop to provide a data signal to the functional flop. In a third mode, the latch circuit is configured to provide a feedback path in order to feed back to the functional flop a signal generated by the functional flop.

Abstract: A scannable flop circuit configured for operation in a multiple modes. The scannable flop circuit includes a functional flop having a data input, a clock input, and a data output, a scan flop having a scan data input and a scan data output, and a latch circuit coupled between the functional flop and the scan flop. The latch circuit includes one or more mode signal inputs to enable selection of an operating mode. In a first mode, the latch circuit is configured to enable the functional flop to provide a data signal to the scan flop. In a second mode, the latch circuit is configured to enable the scan flop to provide a data signal to the functional flop. In a third mode, the latch circuit is configured to provide a feedback path in order to feed back to the functional flop a signal generated by the functional flop.