Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

Abstract: A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

Abstract: A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.

Abstract: A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.

Abstract: A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.

Abstract: A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.

Abstract: A pre-charge triggering technique used in connection with a synchronous pipeline stage (FIG. 1b) that includes an input register (11) that feeds a function section (12) with both non-pre-charged front-end logic (12a) and pre-charged function logic (12b). An output section (13) includes pre-charge control logic that activates a PRECHARGE line (21) to provide a PRECHARGE signal at the beginning of the pre-charge phase, i.e., at the end of the active phase. The input register is triggered (21) when the PRECHARGE line is switched active, before the next rising clock edge, so that the next active phase begins prior to the beginning of the next clock cycle, and prior to the end of the pre-charge phase of the current clock cycle (FIG. 1d).

Abstract: An amplifier is arranged with an actively clamped load. In a differential amplifier, a pair of emitter-coupled transistors has loads connected between the collectors and a voltage supply. Separate clamping transistors have their collector-emitter paths connected across respective ones of the loads. A clamping control circuit, responsive to an input signal, produces a variable control signal to clamp output signal swings across the loads. A similar clamping control circuit can be used with a single-ended amplifier. Such an amplifier having an actively clamped load is useful in sense amplifier circuit arrangements in semiconductor memory arrangements used in data processing systems.

Abstract: An amplifier is arranged with an actively clamped load. In a differential amplifier, a pair of emitter-coupled transistors has loads connected between the collectors and a voltage supply. Separate clamping transistors have their collector-emitter paths connected across respective ones of the loads. A clamping control circuit, responsive to an input signal, produces a variable control signal to clamp output signal swings across the loads. A similar clamping control circuit can be used with a single-ended amplifier. Such an amplifier having an actively clamped load is useful in sense amplifier circuit arrangements in semiconductor memory arrangements used in data processing systems.