Abstract: A method of analyzing a circuit having a structural loop between different channel connected components within the circuit first splits the circuit into its constituent channel connected components (100). The structural loops are then detected and broken (101) before obtaining a pair of boolean functions at each break point (102) by inserting a pair of temporary boolean variables at the break point on a boundary between different channel connected components and analyzing each channel connected component in the structural loop utilizing the pair of temporary boolean variables to obtain the pair of boolean functions representing the functionality of the circuit at the break point. The pair of boolean functions are then analyzed (103) to determine whether the structural loop is sequential in nature, and, if so, the pair of boolean functions is modified (105) in order to remove any dependence in the pair of boolean functions on the pair of boolean variables.

Abstract: A method for deriving a functional circuit description that is independent of pre-charge node values, the functional circuit description IS a transformation of an initial structural circuit description having pre-chargeable nodes. The method includes identifying the pre-chargeable nodes in initial structural circuit description. The pre-chargeable nodes have a logic value that is dependent upon an associated pre-charge clock. Pre-charge nodes value associated with the pre-chargeable nodes are then determined and then the functional circuit description that is independent of pre-charge node values is derived.

Abstract: A method for deriving a hierarchical functional description of a circuit by creating a hierarchical model of the circuit from the initial hardware description (100), the hierarchical model having at least one boundary connection coupling hierarchical levels of the model. Signal flow conflicts at each boundary connection are then analyszd (101) which includes flattening (205) instances of the hierarchical model where signal flow conflicts are identified thereby transforming the hierarchical model into a signal flow conflict free hierarchical model. A hierarchical functional description of the circuit is then derived (102) from the signal flow conflict free hierarchical model.

Abstract: A method for deriving a hierarchical functional description of a circuit by creating a hierarchical model of the circuit from the initial hardware description (100), the hierarchical model having at least one boundary connection coupling hierarchical levels of the model. Signal flow conflicts at each boundary connection are then analysed (101) which includes flattening (205) instances of the hierarchical model where signal flow conflicts are identified thereby transforming the hierarchical model into a signal flow conflict free hierarchical model. A hierarchical functional description of the circuit is then derived (102) from the signal flow conflict free hierarchical model.

Abstract: A method of analyzing a circuit having at least one structural loop within a channel connected component first requires that the circuit be at least partly notionally split into its constituent channel connected components (100). The structural loops within a channel-connected component are then detected and a pair of temporary boolean variables is inserted at a break point in each structural loop in the channel-connected component at an internal input. The channel connected component is then analyzed utilizing the pairs of temporary boolean variables at the break points in order to obtain a pair of boolean equations at each break point representing the functionality of the channel connected component at that break point to produce a system of boolean equations for the break points within the channel connected component (101). The system of boolean equations is then solved to produce a result that indicates whether the channel connected component has oscillatory, combinational or sequential behavior.