Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: A method includes disposing at least one power device between a first direct bonded metal (DBM) substrate and a second DMB substrate and thermally coupling a plurality of pipes to a top side of the first DBM substrate opposite a side of the first DBM substrate with the at least one power device. The plurality of pipes is configured to carry cooling fluids in thermal contact with the first DBM substrate.

Abstract: A semiconductor package assembly having a connecting clip disposed on both a first material stack and a second material stack having different thicknesses and disposed on a conducting substrate. This connecting clip has a first portion disposed on to the first material stack and second portion disposed on the second material stack, such that the surfaces of the first portion and second portion opposite the conducting substrate are at the same perpendicular distance from the conducting substrate. For example, in some implementations, when the thickness of the second material stack is smaller than the thickness of the first material stack, the second portion of the connecting clip may include a vertical support disposed on the second material stack to equalize the heights of the surfaces of the first portion and second portion of the connecting clip.

Abstract: According to an aspect, a power electronic module includes a substrate, a semiconductor die coupled to the substrate, and a clip member configured to secure the semiconductor die to the substrate, where the clip member includes a base portion having a surface coupled to the semiconductor die, an extender portion that extends from the base portion, where the extender portion includes a contact portion coupled to the substrate, and at least one protrusion that extends from the base portion or the extender portion.

Abstract: A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.

Abstract: A semiconductor guide pin is disclosed. Specific implementations may include a heatsink, one or more substrates coupled together, one or more pressfit pins coupled to the one or more substrates, and two or more guide pins coupled to the one or more substrates, where the two or more guide pins may have a height greater than the one or more pressfit pins.

Abstract: In one embodiment, a semiconductor package may be formed having a first side and a second side that is substantially opposite to the first side. An embodiment may include forming an attachment clip extending substantially laterally between the first and second sides wherein the attachment clip is positioned near a distal end of the first and second sides. An embodiment may also include forming the attachment clip to have a flexible main portion that can bend away from a plane of the main portion toward a bottom side of the semiconductor package.

Abstract: A circuit module includes a substrate with a patterned metal surface. The patterned metal surface includes a conductive terminal pad, a first conductive pad, and a second conductive pad that is non-adjacent to the conductive terminal pad. A first circuit portion is assembled on the first conductive pad and a second circuit portion is assembled on the second conductive pad. A conductive bridge electrically couples the conductive terminal pad and the second conductive pad. The conductive bridge includes an elevated span extending above and across the first conductive pad.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: Implementations of semiconductor packages may include a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the lead frame.

Abstract: Implementations of semiconductor packages may include: a first substrate having two or more die coupled to a first side, a clip coupled to each of the two or more die on the first substrate and a second substrate having two or more die coupled to a first side of the second substrate. A clip may be coupled to each of the two or more die on the second substrate. The package may include two or more spacers coupled to the first side of the first substrate and a lead frame between the first substrate and the second substrate and a molding compound. A second side of each of the first substrate and the second substrate may be exposed through the molding compound. A perimeter of the first substrate and a perimeter of the second substrate may not fully overlap when coupled through the two or more spacers.

Abstract: A fin frame baseplate is disclosed. Specific implementations include a baseplate configured to be coupled to a substrate, a fin frame including a base portion coupled to the baseplate, and a plurality of fins extending from the base portion, the plurality of fins protruding from the base portion. The fin frame may include a plurality of openings therethrough.

Abstract: Implementations of a semiconductor package may include: a substrate, a case coupled to the substrate and a plurality of press-fit pins. The press-fit pins are molded into and fixedly coupled with the case. The pins are also electrically and mechanically coupled to the substrate.