Patents by Inventor Ataru Kumagai

Ataru Kumagai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of producing a semiconductor integrated circuit device using a master slice approach
    Patent number: 5506162
    Abstract: A semiconductor integrated circuit device provides; a master chip including a basic cell region having a plurality of basic cell arrays arranged thereon, for forming various kinds of circuits. An input/output cell region provides a plurality of input/output cells arranged along the periphery of the basic cell region. A first wiring layer is formed on the basic cell region and the input/output cell region via a first insulation layer and has contact holes at predetermined positions. The first wiring layer includes fixed wirings irrespective of the kind of circuit to be formed. A second wiring layer is formed on the first wiring layer via a second insulation layer having through holes at predetermined positions. The second wiring layer includes programmed wirings to specify the kind of circuit to be formed.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: April 9, 1996
    Assignee: Fujitsu Limited
    Inventors: Yoshio Hirose, Koichi Yamashita, Shigeki Kawahara, Shinji Sato, Takeshi Sasaki, Ataru Kumagai