Patents by Inventor Atashi Basu

Atashi Basu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240095432
    Abstract: Methods, systems, and computer programs are presented for determining the recipe for manufacturing a semiconductor with the use of machine learning (ML) to accelerate the definition of recipes. One general aspect includes a method that includes an operation for performing experiments for processing a component, each experiment controlled by a recipe, from a set of recipes, that identifies parameters for manufacturing equipment. The method further includes an operation for performing virtual simulations for processing the component, each simulation controlled by one recipe from the set of recipes. An ML model is obtained by training an ML algorithm using experiment results and virtual results from the virtual simulations. The method further includes operations for receiving specifications for a desired processing of the component, and creating, by the ML model, a new recipe for processing the component based on the specifications.
    Type: Application
    Filed: October 31, 2023
    Publication date: March 21, 2024
    Inventors: Kapil Umesh Sawlani, Atashi Basu, David Michael Fried, Michal Danek, Emily Ann Alden
  • Patent number: 11887847
    Abstract: Methods and precursors for selectively depositing a metal film on a silicon nitride surface relative to a silicon oxide surface are described. The substrate comprising both surfaces is exposed to a blocking compound to selectively block the silicon oxide surface. A metal film is then selectively deposited on the silicon nitride surface.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: January 30, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kurt Fredrickson, Atashi Basu, Mihaela A. Balseanu, Ning Li
  • Patent number: 11836429
    Abstract: Methods, systems, and computer programs are presented for determining the recipe for manufacturing a semiconductor with the use of machine learning (ML) to accelerate the definition of recipes. One general aspect includes a method that includes an operation for performing experiments for processing a component, each experiment controlled by a recipe, from a set of recipes, that identifies parameters for manufacturing equipment. The method further includes an operation for performing virtual simulations for processing the component, each simulation controlled by one recipe from the set of recipes. An ML model is obtained by training an ML algorithm using experiment results and virtual results from the virtual simulations. The method further includes operations for receiving specifications for a desired processing of the component, and creating, by the ML model, a new recipe for processing the component based on the specifications.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: December 5, 2023
    Assignee: Lam Research Corporation
    Inventors: Kapil Umesh Sawlani, Atashi Basu, David Michael Fried, Michal Danek, Emily Ann Alden
  • Publication number: 20230170210
    Abstract: Methods and precursors for selectively depositing a metal film on a silicon nitride surface relative to a silicon oxide surface are described. The substrate comprising both surfaces is exposed to a blocking compound to selectively block the silicon oxide surface. A metal film is then selectively deposited on the silicon nitride surface.
    Type: Application
    Filed: November 28, 2022
    Publication date: June 1, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Kurt Fredrickson, Atashi Basu, Mihaela A. Balseanu, Ning Li
  • Patent number: 11621160
    Abstract: A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: April 4, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Eswaranand Venkatasubramanian, Srinivas Gandikota, Kelvin Chan, Atashi Basu, Abhijit Basu Mallick
  • Patent number: 11515151
    Abstract: Methods and precursors for selectively depositing a metal film on a silicon nitride surface relative to a silicon oxide surface are described. The substrate comprising both surfaces is exposed to a blocking compound to selectively block the silicon oxide surface. A metal film is then selectively deposited on the silicon nitride surface.
    Type: Grant
    Filed: October 5, 2018
    Date of Patent: November 29, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Kurt Fredrickson, Atashi Basu, Mihaela Balseanu, Ning Li
  • Publication number: 20220374572
    Abstract: Methods, systems, and computer programs are presented for determining the recipe for manufacturing a semiconductor with the use of machine learning (ML) to accelerate the definition of recipes. One general aspect includes a method that includes an operation for performing experiments for processing a component, each experiment controlled by a recipe, from a set of recipes, that identifies parameters for manufacturing equipment. The method further includes an operation for performing virtual simulations for processing the component, each simulation controlled by one recipe from the set of recipes. An ML model is obtained by training an ML algorithm using experiment results and virtual results from the virtual simulations. The method further includes operations for receiving specifications for a desired processing of the component, and creating, by the ML model, a new recipe for processing the component based on the specifications.
    Type: Application
    Filed: October 22, 2020
    Publication date: November 24, 2022
    Inventors: Kapil Umesh Sawlani, Atashi Basu, David Michael Fried, Michal Danek, Emily Ann Alden
  • Patent number: 11332488
    Abstract: Metal coordination complexes comprising at least one diazabutadiene based ligand having a structure represented by: where R1 and R4 are selected from the group consisting of C4-C10 alkyl groups; and R2 and R3 are each independently selected from the group consisting of H, C1-C6 alkyl, cycloalkyl, or aryl groups and the difference in the number of carbons in R2 and R3 is greater than or equal to 2. Processing methods using the metal coordination complexes are also described.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: May 17, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jeffrey W. Anthis, Atashi Basu, David Thompson, Nasrin Kazem
  • Publication number: 20210358744
    Abstract: A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film.
    Type: Application
    Filed: August 2, 2021
    Publication date: November 18, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Eswaranand Venkatasubramanian, Srinivas Gandikota, Kelvin Chan, Atashi Basu, Abhijit Basu Mallick
  • Patent number: 11094533
    Abstract: A microelectronic device on a semiconductor substrate comprises: a gate electrode; and a spacer adjacent to the gate electrode, the spacer comprising: a the low-k dielectric film comprising one or more species of vanadium oxide, which is optionally doped, and an optional silicon nitride or oxide film. Methods comprise depositing a low-k dielectric film optionally sandwiched by a silicon nitride or oxide film to form a spacer adjacent to a gate electrode of a microelectronic device on a semiconductor substrate, wherein the low-k dielectric film comprises a vanadium-containing film.
    Type: Grant
    Filed: October 2, 2019
    Date of Patent: August 17, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Eswaranand Venkatasubramanian, Srinivas Gandikota, Kelvin Chan, Atashi Basu, Abhijit Basu Mallick
  • Patent number: 11078224
    Abstract: Metal coordination complexes comprising at least one diazabutadiene based ligand having a structure represented by: where A1, A2, A3, and A4 are atoms in a 6-membered ring and are independently selected from C, N, O, S, and P; and where R1, R2, R3, R4, R5, and R6 are independently selected from the group consisting of H, amino groups, C1-C6 alkyl groups, or C4-10 cycloalkyl groups; and further provided that alkyl groups may optionally contain silicon; and where the metal coordination complex is capable of participating in a Diels-Alder type reaction with a dienophile. Processing methods using the metal coordination complexes are also described.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: August 3, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Jeffrey W. Anthis, Atashi Basu
  • Patent number: 11049722
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: June 29, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 10977405
    Abstract: Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: April 13, 2021
    Assignee: Lam Research Corporation
    Inventors: Michael Bowes, Atashi Basu, Kapil Sawlani, Dongyao Li, Anand Chandrashekar, David M. Fried, Michal Danek
  • Publication number: 20200377538
    Abstract: Metal coordination complexes comprising at least one diazabutadiene based ligand having a structure represented by: where R1 and R4 are selected from the group consisting of C4-C10 alkyl groups; and R2 and R3 are each independently selected from the group consisting of H, C1-C6 alkyl, cycloalkyl, or aryl groups and the difference in the number of carbons in R2 and R3 is greater than or equal to 2. Processing methods using the metal coordination complexes are also described.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Jeffrey W. Anthis, Atashi Basu, David Thompson, Nasrin Kazem
  • Patent number: 10811250
    Abstract: Methods for depositing silicon nitride films with higher nitrogen content are described. Certain methods comprise exposing a substrate to a silicon-nitrogen precursor and ammonia plasma to form a flowable polymer, and then curing the polymer to form a silicon nitride film. Certain methods cure the flowable polymer without the use of a UV-cure process. Also described is the film generated by the methods described above.
    Type: Grant
    Filed: July 5, 2018
    Date of Patent: October 20, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Atashi Basu, Srinivas D. Nemani, Ellie Y. Yieh
  • Publication number: 20200312653
    Abstract: Methods and precursors for selectively depositing a metal film on a silicon nitride surface relative to a silicon oxide surface are described. The substrate comprising both surfaces is exposed to a blocking compound to selectively block the silicon oxide surface. A metal film is then selectively deposited on the silicon nitride surface.
    Type: Application
    Filed: October 5, 2018
    Publication date: October 1, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Kurt Fredrickson, Atashi Basu, Mihaela Balseanu, Ning Li
  • Patent number: 10752649
    Abstract: Metal coordination complexes comprising at least one diazabutadiene based ligand having a structure represented by: where R1 and R4 are selected from the group consisting of C4-C10 alkyl groups; and R2 and R3 are each independently selected from the group consisting of H, C1-C6 alkyl, cycloalkyl, or aryl groups and the difference in the number of carbons in R2 and R3 is greater than or equal to 2. Processing methods using the metal coordination complexes are also described.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: August 25, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey W. Anthis, Atashi Basu, David Thompson, Nasrin Kazem
  • Publication number: 20200242209
    Abstract: Provided herein are systems and methods for optimizing feature fill processes. The feature fill optimization systems and methods may be used to optimize feature fill from a small number of patterned wafer tests. The systems and methods may be used for optimizing enhanced feature fill processes including those that include inhibition and/or etch operations along with deposition operations. Results from experiments may be used to calibrate a feature scale behavioral model. Once calibrated, parameter space may be iteratively explored to optimize the process.
    Type: Application
    Filed: January 29, 2019
    Publication date: July 30, 2020
    Inventors: Michael Bowes, Atashi Basu, Kapil Sawlani, Dongyao Li, Anand Chandrashekar, David M. Fried, Michal Danek
  • Publication number: 20200234959
    Abstract: Methods of modifying the threshold voltage of metal oxide stacks are discussed. These methods utilize materials which provide larger shifts in threshold voltage while also being annealed at lower temperatures.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Siddarth Krishnan, Rajesh Sathiyanarayanan, Atashi Basu, Paul F. Ma
  • Patent number: 10699952
    Abstract: Methods comprising depositing a film material to form an initial film in a trench in a substrate surface are described. The film is treated to expand the film to grow beyond the substrate surface.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: June 30, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Atashi Basu, Abhijit Basu Mallick, Ziqing Duan, Srinivas Gandikota