Abstract: System and method for adaptively optimizing digital-to-analog converter input range values for improved signal-to-noise ratio for analog-in-memory computing (AIMC) systems. The method includes a step of tuning the input ranges of the digital-to-analog (DAC) converters of a “tile”, comprised of Processing Elements (PEs) in a crossbar arrangement, to minimize the matrix-vector-multiplication (MVM) error under the presence of some residual noise term that is applied to the output of the MVM. Alternatively, the method includes tuning the input ranges of the DAC converters to minimize the accuracy of a predefined task, e.g., a classification task, under the presence of some residual noise term applied to the output of each matrix-vector-multiplication. The DAC input value range is optimized with respect to a metric that depends on a residual noise source present in AIMC systems. In an embodiment, the system minimizes the error introduced by the residual noise and the quantization.

Abstract: A computer-implemented method and device performing digital post-processing of an in-memory computing crossbar array. The computer-implemented method includes providing a digital computing block positioned at a periphery of the in-memory computing crossbar array. The digital computing block is configured to perform fixed-point computations of an input, compression on the fixed-point computations of the input; and a nonlinear activation function.

Abstract: System and method for adaptively optimizing digital-to-analog converter input range values for improved signal-to-noise ratio for analog-in-memory computing (AIMC) systems. The method includes a step of tuning the input ranges of the digital-to-analog (DAC) converters of a “tile”, comprised of Processing Elements (PEs) in a crossbar arrangement, to minimize the matrix-vector-multiplication (MVM) error under the presence of some residual noise term that is applied to the output of the MVM. Alternatively, the method includes tuning the input ranges of the DAC converters to minimize the accuracy of a predefined task, e.g., a classification task, under the presence of some residual noise term applied to the output of each matrix-vector-multiplication. The DAC input value range is optimized with respect to a metric that depends on a residual noise source present in AIMC systems. In an embodiment, the system minimizes the error introduced by the residual noise and the quantization.

Abstract: A matrix-vector multiplication device includes an input encoder that encodes an input vector into a binary complement format value and a binary true format value; a pulse generator that converts each encoded bit of the binary complement format value and each encoded bit of the binary true format value into a corresponding pulse signal; a crossbar array of weights, wherein each weight is encoded as a differential analog conductance of resistive memory devices, wherein the pulse generator simultaneously applies a pulse signal corresponding to a given encoded bit of the binary complement format value and a pulse signal corresponding to a given encoded bit of the binary true format value to corresponding resistive memory devices; an analog-to-digital converter that digitizes outputs of the crossbar array of weights to generate partial dot-product results; and a digital counter that computes a final dot-product result from the partial dot-product results.

Abstract: An analog in-memory computing (AIMC) system includes a plurality of tiles. A plurality of vertically stacked tiers are present on each tile. Each tier comprises a crossbar of resistive memory devices, configured to encode a matrix of weights. A digital to analog convert (DAC) is shared by the plurality of tiles. The DAC is configured to encode an input vector to voltage pulses applied on the crossbar. An analog to digital converter (ADC) is shared by the plurality of tiles, and includes a register of counters. The ADC is configured to measure an induced current on each column of the crossbar and digitize the induced current into a digital value. A programmable logic controller is configured to: control the ADC to retain integration values between integrations performed for each tier. An accumulation of partial integration results is performed in-situ of the tile.

Abstract: According to one embodiment, a method, computer system, and computer program product for routing acceleration in mixture of experts ensembles is provided. The present invention may include receiving input data at a router; generating a plurality of output vectors by applying a routing function to the input data, wherein each output vector is associated with one or more respective tiles or pairs of tiles in a plurality of MVM tiles; determining a plurality of sub-vectors in the output vectors, wherein each sub-vector in the plurality of sub-vectors is associated with a respective output vector in the plurality of output vectors, and merging the sub-vectors into an element vector; generating a probability distribution vector by applying a Softmax function to the element vector and determining the largest elements of the probability distribution; and configuring the router based on the one or more largest elements of the probability distribution.

Abstract: A method for balancing utilization of tiles in an analog in-memory computing system includes identifying, by a computer processor, a plurality of tiles in the analog in-memory computing system. The computer processor receives a plurality of layers in a neural network being processed by the analog in-memory computing system. The computer processor maps the plurality of layers in the neural network to the plurality of tiles. The computer processor determines a number of operations for each of the tiles in the plurality of tiles. The computer processor determines an equalized utilization rate for the tiles in the plurality of tiles. In addition, the computer processor assigns the layers to the plurality of tiles. The tiles are assigned so that a first utilization rate of a first tile is balanced relative to a second utilization rate of a second tile in the analog in-memory computing system.

Abstract: The present disclosure relates to a method for compensating non-ideality of a neuromorphic memory device. The neuromorphic memory device comprising a crossbar array of wordlines and bitlines. The crossbar array comprises a block of wordline and bitline segments, wherein memory elements of the block are programmed to represent array values. The device is configured for applying a set of inputs to the initial wordlines for performing dot products. The method comprises: performing at least one of: wordline expansion or bitline expansion of the block. The set of inputs may be applied to the initial wordlines of the expanded block and in case the bitline expansion is performed an additional input may be applied to the additional wordlines of the expanded block. The currents flowing in the bitlines of the expanded block may be measured. The dot products may be determined using the measured currents.

Abstract: The invention is notably directed to a method of programming memory elements of an in-memory computing (IMC) device. The IMC applies a SET signal to the K memory elements of said each cell to set each of the K memory elements to a SET state and reading K conductance values of the K memory elements in the SET state. The IMC adjusts, based on the K conductance values read and the target conductance value, a conductance value of at least one of the K memory elements to match a summed conductance of the K memory elements of said each cell with the target conductance value. The IMC maximizes a number of the K memory elements that are either in their SET state or in a RESET state of zero conductance nominal value, such that at most one of the K memory elements is neither in a SET state nor in a RESET state.

Abstract: The present disclosure relates to a method for compensating non-ideality of a neuromorphic memory device. The neuromorphic memory device comprising a crossbar array of wordlines and bitlines. The crossbar array comprises a block of wordline and bitline segments, wherein memory elements of the block are programmed to represent array values. The device is configured for applying a set of inputs to the initial wordlines for performing dot products. The method comprises: performing at least one of: wordline expansion or bitline expansion of the block. The set of inputs may be applied to the initial wordlines of the expanded block and in case the bitline expansion is performed an additional input may be applied to the additional wordlines of the expanded block. The currents flowing in the bitlines of the expanded block may be measured. The dot products may be determined using the measured currents.

Abstract: The invention is notably directed to a method of programming memory elements of an in-memory computing (IMC) device. The IMC applies a SET signal to the K memory elements of said each cell to set each of the K memory elements to a SET state and reading K conductance values of the K memory elements in the SET state. The IMC adjusts, based on the K conductance values read and the target conductance value, a conductance value of at least one of the K memory elements to match a summed conductance of the K memory elements of said each cell with the target conductance value. The IMC maximizes a number of the K memory elements that are either in their SET state or in a RESET state of zero conductance nominal value, such that at most one of the K memory elements is neither in a SET state nor in a RESET state.