Abstract: In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing.

Abstract: In one embodiment of the invention, a method of analyzing a circuit design is disclosed. In the method of analyzing a circuit design, a circuit is levelized into multiple levels. Circuit simulations of elements at a level are determined using circuit simulators, one for each element and in parallel in level order. Topological circuit loops may be removed from the circuit. Circuit simulation of the circuit may be performed on the circuit using the circuit simulations determined by the circuit simulators at each level of the circuit.

Abstract: The present invention is directed to a method and apparatus for accurately estimating signal delays of an electrical circuit by taking into account both resistance and capacitance of an interconnect network when determining both gate delays and interconnect delays of the circuit. Exemplary embodiments of the present invention, by providing a highly accurate estimate of signal delays, result in highly efficient, cost-effective electrical circuit design and fabrication. Further, a high degree of customer satisfaction can be realized because the possibility that a given electrical circuit will not comply with customer specified time constraints is minimal.

Abstract: In a computer aided design system for assisting in the design and analysis of integrated circuits, users can specify an integrated circuit using either a conventional circuit component netlist, or an HDL circuit description. Timing constraints are specified using conventional system level timing constraints, at least one clock timing constraint and a plurality multi-cycle timing constraints specifying clock based timing constraints for the transmission of data between sequential data elements in which at least a subset of the clock based timing constraints concern timing constraints for duration longer than a single clock period. In addition, the user may provide the system with a plurality of constraint based timing path specifications, each indicating signal paths through the integrated circuit to which specified ones of the multi-cycle timing constraints are applicable and signal paths to which the specified ones of the multi-cycle timing constraints are not applicable.

Abstract: A computer aided design system converts system level timing constraints to the minimum number of path-based timing constraints necessary to represent the same timing constraints as the system level timing constraints. Using a data structure for each node of the circuit, signal arrival times and required arrival times for each node are generated for each high level timing constraint, and the worst slack time is identified for each node. Then, a node with a worst slack time is selected, the constraint associated with that worst slack time is identified, and then a worst case path from a start node of the identified constraint through the selected node to an end node of the identified constraint is determined. The start and required signal arrival times associated with the identified constraint's start and end nodes in the determined path are also identified.

Abstract: The present invention is directed to a method of designing and fabricating a circuit layout which revolutionizes the manner by which critical weights of a circuit layout are assessed. In accordance with exemplary embodiments, a critical path is assessed on the basis of both a physical delay associated with a data propagation path and with respect to any clock skew which exists with respect to the data propagation path. A critical path can be a path having the shortest physical length from an input node to an output node if the clock skew along this path results in a high probability of a race condition. In accordance with exemplary embodiments, clock skew is assessed by determining the time differential between the arrival of a clock signal at a given data source instance and the arrival of a clock signal at a given data destination instance.

Abstract: The invention accepts user input that describes the circuit elements of a digital circuit and the interconnections between those elements. Based upon the user input, the invention computes the maximum setup and hold times for each data input of the integrated circuit. First, maximum and minimum delays from the clock inputs to the storage elements on the integrated circuit. Similarly, the maximum and minimum delays from the data inputs of the integrated circuit to each level one storage element are determined where a level one storage element is defined as a storage element that has no other storage elements interposed between it and a data input. For each data input/level one storage element pair, the setup time is computed based upon the previously calculated maximum data delay and minimum clock delay and the required setup time for the element. The desired setup time for a data input is the maximum setup time over all the level one storage elements coupled to that data input.