Abstract: A repeater circuit includes at least a first input, and output, and a repeater. The first input for receiving a single-ended data signal from an embedded universal serial bus (eUSB) host. The output provides a differential data signal in a differential universal serial bus (USB) format. The repeater is coupled between the first input and output for converting the single-ended data signal to a differential data signal, the repeater includes an adaptive delay element operable for both sides of the differential data signal to delay one, but not both, of a rising edge and a falling edge of the differential data signal in order to meet a crossover specification for the USB format.

Abstract: A repeater circuit includes at least a first input, and output, and a repeater. The first input for receiving a single-ended data signal from an embedded universal serial bus (eUSB) host. The output provides a differential data signal in a differential universal serial bus (USB) format. The repeater is coupled between the first input and output for converting the single-ended data signal to a differential data signal, the repeater includes an adaptive delay element operable for both sides of the differential data signal to delay one, but not both, of a rising edge and a falling edge of the differential data signal in order to meet a crossover specification for the USB format.

Abstract: A driver circuit includes an output terminal adapted for driving a data signal through a coupling capacitor to an external device. A first transistor is employed to drive the signal, and an N-type metal-oxide semiconductor (NMOS) transistor couples power to the first transistor. The NMOS transistor includes a first terminal connected to a positive terminal of a voltage supply, a second terminal coupled to an output terminal through a termination resistor, a gate terminal, and a bulk terminal connected to the negative terminal of the voltage supply. A charge pump circuit supplies a voltage to a gate terminal of the NMOS transistor, and is operable to provide a first voltage higher than that of the voltage supply to activate the NMOS device, and, responsive to detecting a ramp-down of the supply voltage, transition to providing the supply voltage to the NMOS device gate terminal.

Abstract: Implementations of a pre-emphasis signal processing system may include an output driver which may include a pre-emphasis transistor coupled with a steady state transistor, where gates of the pre-emphasis transistor and steady state transistor may be coupled together. The system may include a regulator voltage input coupled to a source of the pre-emphasis transistor; a first resistor coupled between a drain of the pre-emphasis transistor and an output of the output driver; and a second resistor coupled between the drain of the steady state transistor and the output of the output driver; and a pre-emphasis source including a current source coupled to a delay transistor, the delay transistor coupled with the output of the output driver.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface having a first bi-directional channel and a second bi-directional channel. The interface operates in one of a first operational state and a second operational state, and performs an exemplary power-saving scheme if it is operating in the second operational state. The interface may detect a plurality of power states and initiate the power-saving scheme based on the detected power state. The plurality of power states may comprise a first power state (low current mode), a second power state (high current mode), and a third power state (mid-current mode).

Abstract: Interface circuit. Example interface circuits may be used for data transfer in accordance with the USB protocol version 3.2 or higher. Example interface circuits are configured to enable cooperation with a sink device and/or a host device having a lower supply voltage than the interface circuit, and reducing or preventing voltage spikes herein after power-on reset (POR) events. Thereto, the detection circuit for detection of a sink device downstream of the interface circuit is provided with a signal path for use during a first period after the POR event and having a resistance larger than a resistance used during detection of the said sink device.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface having a first bi-directional channel and a second bi-directional channel. The interface operates in one of a first operational state and a second operational state, and performs an exemplary power-saving scheme if it is operating in the second operational state. The interface may detect a plurality of power states and initiate the power-saving scheme based on the detected power state. The plurality of power states may comprise a first power state (low current mode), a second power state (high current mode), and a third power state (mid-current mode).

Abstract: Various embodiments of the present technology may provide methods and apparatus for an output buffer. The output buffer is configured to perform in both a DP mode and an HDMI mode, as well as meet certain compliance conditions in an HDMI compliance testing mode. The output buffer includes a plurality of transistors and resistors arranged to operate in DP mode and HDMI mode. The plurality of transistors and resistors are arranged to reduce leakage current during the HDMI compliance testing mode.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured to detect a hot unplug condition based on a first output voltage at an output terminal of a first buffer circuit and a second output voltage at an output terminal of a second buffer circuit, wherein the first and second buffer circuits receive a common input. The interface may further detect the hot unplug condition based on a difference of a peak magnitude of the first output voltage and a peak magnitude of the second output voltage.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured to detect a hot unplug condition based on a first output voltage at an output terminal of a first buffer circuit and a second output voltage at an output terminal of a second buffer circuit, wherein the first and second buffer circuits receive a common input. The interface may further detect the hot unplug condition based on a difference of a peak magnitude of the first output voltage and a peak magnitude of the second output voltage.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an output buffer. The output buffer is configured to perform in both a DP mode and an HDMI mode, as well as meet certain compliance conditions in an HDMI compliance testing mode. The output buffer includes a plurality of transistors and resistors arranged to operate in DP mode and HDMI mode. The plurality of transistors and resistors are arranged to reduce leakage current during the HDMI compliance testing mode.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an auxiliary channel. The auxiliary channel may include a first PMOS transistor connected between two terminals of the auxiliary channel and a second PMOS transistor connected to one of the two terminals, via a resistor, at a first end and to a gate terminal of the first PMOS. The auxiliary channel may further include a support circuit connected to the gate terminals of both the first and second PMOS transistors.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage, bi-directional channel redriver having a transmitter and a receiver that share input pads and output pads. The interface may provide for selective biasing of the transmitter and receiver using a switching circuit and a resistance circuit connected to the channel's input and output pads.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage interface and provide a redriver connected between a pair of input pads and a pair of output pads. The interface may further provide a signal detection circuit connected to the pair of input pads and configured to bias a pair of input termination resistors connected to the input pads with one of a supply voltage and a regulator voltage. The signal detection circuit may be further configured to enable/disable the redriver for a period of time.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage interface and provide a redriver connected between a pair of input pads and a pair of output pads. The interface may further provide a signal detection circuit connected to the pair of input pads and configured to bias a pair of input termination resistors connected to the input pads with one of a supply voltage and a regulator voltage. The signal detection circuit may be further configured to enable/disable the redriver for a period of time.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage, bi-directional channel redriver having a transmitter and a receiver that share input pads and output pads. The interface may provide for selective biasing of the transmitter and receiver using a switching circuit and a resistance circuit connected to the channel's input and output pads.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage, bi-directional channel redriver having a transmitter and a receiver that share input pads and output pads. The interface may provide for selective biasing of the transmitter and receiver using a switching circuit and a resistance circuit connected to the channel's input and output pads.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage, bi-directional channel redriver having a transmitter and a receiver that share input pads and output pads. The interface may provide for selective biasing of the transmitter and receiver using a switching circuit and a resistance circuit connected to the channel's input and output pads.

Abstract: A power supply monitoring circuit that monitors and delivers the highest voltage power supply to an IC system includes a voltage comparator that receives two different power supply voltages, and outputs a first signal to the gate of a first switching transistor connected between a first power supply and an system power supply output node. The comparator output is also input to an inverter, the output of which comprises a second signal connected to the gate of a second switching transistor connected between a second power supply and the system power supply output node. When the first supply voltage exceeds the second supply voltage, the first transistor is switched on to connect the first supply to the system output node, and the second transistor is switched off; and vice versa. The comparator includes designed-in hysteresis to prevent simultaneous switching of the two transistors.