Abstract: A data storage device including, in one implementation, a memory device and a controller configured to configured to retrieve a plurality of physical memory addresses from a first lookup table in the non-volatile memory. Each physical memory address is a combination of a word line and a string number of the non-volatile memory and the each physical memory address has a first number of bits. The controller is further configured to generate a plurality of encoded values by encoding the plurality of physical memory addresses. Each of the plurality of encoded values has a second number of bits that is smaller than the first number of bits. The controller is further configured to store the plurality of encoded values in the first lookup table, generate a logical to encoded value look-up table with the plurality of encoded values, and store the logical to encoded value look-up table in the memory.

Abstract: Aspects of a storage device are provided that allows a controller to prevent message pointers from being stored in controller memory prior to associated messages due to race conditions, bus arbitration, or similar circumstances. The storage device may include hardware that routes order-sensitive transactions including messages to a first memory and order-sensitive transactions including message pointers to a second memory. The messages and message pointers may be provided from a first processor of the controller to a second processor of the controller. The hardware may hold delivery of each message pointer to the second memory until a delivery acknowledgement of an associated message is received from the first memory. The hardware may also route order-insensitive transactions including other instructions to a third memory different than the first and second memories without holding delivery.

Abstract: A data storage device including, in one implementation, a memory device and a controller configured to configured to retrieve a plurality of physical memory addresses from a first lookup table in the non-volatile memory. Each physical memory address is a combination of a word line and a string number of the non-volatile memory and the each physical memory address has a first number of bits. The controller is further configured to generate a plurality of encoded values by encoding the plurality of physical memory addresses. Each of the plurality of encoded values has a second number of bits that is smaller than the first number of bits. The controller is further configured to store the plurality of encoded values in the first lookup table, generate a logical to encoded value look-up table with the plurality of encoded values, and store the logical to encoded value look-up table in the memory.

Abstract: Aspects of a storage device are provided that allows a controller to prevent message pointers from being stored in controller memory prior to associated messages due to race conditions, bus arbitration, or similar circumstances. The storage device may include hardware that routes order-sensitive transactions including messages to a first memory and order-sensitive transactions including message pointers to a second memory. The messages and message pointers may be provided from a first processor of the controller to a second processor of the controller. The hardware may hold delivery of each message pointer to the second memory until a delivery acknowledgement of an associated message is received from the first memory. The hardware may also route order-insensitive transactions including other instructions to a third memory different than the first and second memories without holding delivery.

Abstract: Memories using end-to-end data protection using physical location checks are described. In one aspect, a storage device includes non-volatile memory and a controller coupled to the memory. The controller may receive a write instruction including a data word and a logical address, include metadata with the word including error correction data, identify a physical address in a mapping table based on the logical address, generate a tag corresponding to the physical address, and replace the error correction data with the generated tag or a value based thereon before writing the data word to memory. In one embodiment, the controller may generate the tag concurrently with performing a logical error check using the error correction data.

Abstract: Aspects of a storage device including a controller memory, a die memory, and a plurality of accumulators corresponding to individual DQs are provided for accelerated DQ training and error detection. A controller stores first data in the controller memory, transfers second data to the die memory over an n-bit bus, and receives n bits of the second data from the die memory based on a DQS. The controller then compares n bits of the first data with n bits of the second data to produce n bit results received into respective accumulators, and the controller simultaneously updates different accumulators in response to bit mismatches. During DQ training, if an accumulator value meets a mismatch threshold, the controller modifies a DQS-DQ timing accordingly. During error detection of a read scrambled page, if an accumulator value does not meet an entropy threshold, the controller identifies an error associated with the page.

Abstract: Aspects of a storage device including a memory and a controller are provided which prevent retransmissions of set features commands with identical read voltage threshold offsets for the same die. When the controller receives a first read command for data stored in the memory, the controller identifies a first parameter to modify a first read threshold, and executes a first set features command for modifying the read threshold based on the first parameter. Subsequently, when the controller receives a second read command from the host device for data stored in the memory, the controller identifies a second parameter to modify a second read threshold, and determines whether the first and second parameters are the same. If the parameters are the same, the controller refrains from executing a second set features command for modifying the second read threshold. Thus, the read latency of the storage device may be reduced.

Abstract: Aspects of a storage device including a controller memory, a die memory, and a plurality of accumulators corresponding to individual DQs are provided for accelerated DQ training and error detection. A controller stores first data in the controller memory, transfers second data to the die memory over an n-bit bus, and receives n bits of the second data from the die memory based on a DQS. The controller then compares n bits of the first data with n bits of the second data to produce n bit results received into respective accumulators, and the controller simultaneously updates different accumulators in response to bit mismatches. During DQ training, if an accumulator value meets a mismatch threshold, the controller modifies a DQS-DQ timing accordingly. During error detection of a read scrambled page, if an accumulator value does not meet an entropy threshold, the controller identifies an error associated with the page.

Abstract: Aspects of a storage device including a memory and a controller are provided which prevent retransmissions of set features commands with identical read voltage threshold offsets for the same die. When the controller receives a first read command for data stored in the memory, the controller identifies a first parameter to modify a first read threshold, and executes a first set features command for modifying the read threshold based on the first parameter. Subsequently, when the controller receives a second read command from the host device for data stored in the memory, the controller identifies a second parameter to modify a second read threshold, and determines whether the first and second parameters are the same. If the parameters are the same, the controller refrains from executing a second set features command for modifying the second read threshold. Thus, the read latency of the storage device may be reduced.

Abstract: Aspects of the disclosure provide a solid state device that includes a non-volatile memory and a controller. The controller includes a processor, a memory, and a direct memory access (DMA) circuitry. The memory comprises a plurality of addresses. The DMA circuitry is configured to receive a first read request for data stored at a first address of the memory; determine whether the first address is an address from the plurality of addresses; when the first address is amongst the plurality of addresses, provide a first response comprising a particular data, without retrieving data stored at the first address; and when the first address is not amongst the plurality of addresses, retrieve the data stored at the first address, and provide a first response comprising the data retrieved from the first address.

Abstract: Aspects of the disclosure provide a solid state device that includes a non-volatile memory and a controller. The controller includes a processor, a memory, and a direct memory access (DMA) circuitry. The memory comprises a plurality of addresses. The DMA circuitry is configured to receive a first read request for data stored at a first address of the memory; determine whether the first address is an address from the plurality of addresses; when the first address is amongst the plurality of addresses, provide a first response comprising a particular data, without retrieving data stored at the first address; and when the first address is not amongst the plurality of addresses, retrieve the data stored at the first address, and provide a first response comprising the data retrieved from the first address.

Abstract: A method and apparatus for performing operations of an electrical device, whereby the apparatus performs operations during operation of a clock producing a clock signal, asserts a reset of components performing operations for the electrical device, stops the clock through a reset generation block for a number N cycles and performs the reset of operations during the stopping of the clock through the reset generation block for the number N cycles.

Abstract: A method and apparatus for performing operations of an electrical device, whereby the apparatus performs operations during operation of a clock producing a clock signal, asserts a reset of components performing operations for the electrical device, stops the clock through a reset generation block for a number N cycles and performs the reset of operations during the stopping of the clock through the reset generation block for the number N cycles.

Abstract: Embodiments of the present invention disclose a method for managing communication from a sender to a receiver. The method comprises receiving a deposit from the sender in favor of the receiver for communicating with the receiver, refunding of the deposit by the receiver in favor of the sender in response to the receiver responding to the communication, and forfeiting of the deposit by the receiver in response to the receiver rejecting the communication, thereby facilitating controlling of nuisance communication. In addition, embodiments of the present invention disclose a method for managing communications from a sender to a recipient.

Abstract: Embodiments of the present invention relate to method and apparatus for pricing at least one of a new product, service or solution. The method comprises launching the new product, service or solution at an initial price, iteratively varying the initial price corresponding to quantities demanded based on a real time feedback, generating a demand schedule by capturing the quantities demanded and correspondingly varying prices, tracing a demand curve based on the demand schedule in real time, determining a demand function and a corresponding demand equation based on the demand curve and repeating step b to reach a point on the demand curve at which the profit margin is a maximum.

Abstract: Embodiments of the present invention generally relate to a method for remotely managing imaging. The method comprises remotely controlling capture of images, remotely monitoring the controlled capture of images and locally and remotely processing the captured images, wherein the processing the captured images comprises analyzing the captured images, recommending control information for recapture of images based on the analysis of the captured images, tracking efficacy of the recaptured images based on the recommendations, and post-processing the recaptured images.

Abstract: An electronic system (1400) includes a processor (1422, 2610) having a pipeline, a bus (2655) coupled to the pipeline, a storage (1435, 1440, 2650) coupled to the bus (2655), the storage (1435, 2650) having a real time operating system (RTOS) and a real-time application, a non-real-time operating system (HLOS), a secure environment kernel (SE), and a software monitor (2310); and protective circuitry (2460) coupled to the processor and operable to establish a first signal (VP1_Active) and a second signal (NS) each having states and together having combinations of the states representing a first category (2430) for the real-time operating system and the real-time application, a second category (2420) for the non-real-time operating system, and a third category (2450) for the secure environment kernel.

Abstract: A method and system for minimizing bit stress in a non-volatile memory during an erase operation are disclosed, which can increase the absolute value of the gate voltage of a memory cell incrementally with each subsequent high voltage erase pulse during the erase operation, instead of ramping up the absolute value of the gate voltage completely during each pulse. Also, each high voltage pulse can be conditioned so that its leading edge does not transition too quickly. Furthermore, a state machine for a flash memory device is disclosed, which can perform, among other things, the erase functions and/or algorithms used for the flash memory.