Abstract: In one embodiment, an image is created by combining an overlay image with a main image. Each pixel of the main and overlay images is defined by a luma component and at least one color component. Each luma component takes a value within a luma range, the lowest and highest values in the luma range being, respectively, a minimum and maximum value. For each pixel in the overlay image, it is determined that the pixel is: an opaque pixel, a transparent pixel, or an intermediate pixel. Each pixel of the main image that is in a location that corresponds to the location of an opaque pixel is replaced with the corresponding opaque pixel. In one embodiment, each pixel of the main image that is in a location that corresponds to the location of a transparent pixel is retained.

Abstract: A method and apparatus for high speed addressing of a memory space from a relatively small address space. An N-bit bus interfaces with a memory device having a 2M address memory space, where M is greater than N. The method and apparatus provide for (a) providing at least two registers, (b) receiving one byte of a plurality of N-bit bytes that together define an address in the memory space, (c) incrementing a count as a result of completing step (b), (d) addressing one of the two registers according to the incremented count in step (c), and (e) storing the one byte in the register addressed in step (d).

Abstract: In a method, a plurality of scale factors and a plurality of sets of pixel replication sequences are provided. A scale factor, a pixel replication sequence, a first pixel of an original image, and a scale offset parameter are selected. The selected first pixel is mapped into a first pixel location in an enlarged image. The selected scale factor and scale offset are added, producing a first sum. The first sum is compared to a maximum sum. If the first sum is less than the maximum sum, the selected first pixel is also mapped into a second pixel location. Otherwise, a second pixel is selected from the original image and mapped into the second pixel location.

Abstract: A memory efficient method and apparatus for displaying large overlaid camera images. According to one aspect of the invention, overlay image data are stored in a memory, fetched, up-scaled, and then combined with main image data to form composite image data for rendering on a graphics display device. According to another aspect of the invention, the overlay image data are stored in a memory, fetched, and then combined with main image data streamed from a source of the main image data.

Abstract: A power cut-off protection control circuit and method. A memory pair and a selecting circuit are provided. The memory pair stores data made available at respective storage inputs of first and second storage elements of the pair and provides the stored data at respective storage outputs thereof. The memory pair has a polarity selecting input through which the output of one of the first and second storage elements is caused to correspond to a first control state of the switch and the output of the other of the first and second storage elements is caused to correspond to a second control state of the switch. The selecting circuit has inputs coupled to the respective storage outputs of the memory pair and an output coupled to a control line of the switch for controlling the switch. A selecting line of the selecting circuit selects between the inputs, for selecting one or the other of the storage outputs of the first and second storage elements.

Abstract: In one embodiment, an image is created by combining an overlay image with a main image. Each pixel of the main and overlay images is defined by a luma component and at least one color component. Each luma component takes a value within a luma range, the lowest and highest values in the luma range being, respectively, a minimum and maximum value. For each pixel in the overlay image, it is determined that the pixel is: an opaque pixel, a transparent pixel, or an intermediate pixel. Each pixel of the main image that is in a location that corresponds to the location of an opaque pixel is replaced with the corresponding opaque pixel. In one embodiment, each pixel of the main image that is in a location that corresponds to the location of a transparent pixel is retained.

Abstract: Provided is a method and apparatus for generating a single header from a stream of image data. A first frame of image data of the stream of image data is received by a graphics controller, which generates the header. The header is then stored in buffers of a memory of the graphics controller. Subsequently, encoded image data of the first frame of image data and subsequent frames of image data are stored at an offset from the header within the buffers. Thereafter, when a processor decodes the encoded image data, the processor retrieves the contents of the buffer having the header of the first frame of image data and encoded image data.

Abstract: A system and method for continuously tracing transfer rectangles for performing image data transfers includes a display controller with control logic, a rectangle module, and a coordinates module. The rectangle module detects write operations to on-screen data in a video memory, and then updates a primary transfer rectangle during a normal mode to include pixel data from the foregoing write operations. The coordinates module stores the primary transfer rectangle for performing a current transfer operation. The coordinates module enters a pause mode before initiating the current transfer operation, and retains the primary transfer rectangle during the pause mode. The coordinate module also stores a secondary transfer rectangle formed during the pause mode by detecting the foregoing write operations. The controller logic instructs the coordinates module to resume the normal mode after the current transfer operation concludes.

Abstract: The invention is directed to expanding digital image data to create enlarged images for display. The images are enlarged in a way in which a selected pixel in an original image is maintained at a particular location in each of the enlarged images regardless of the scale factor used. In a method, a plurality of scale factors and a plurality of sets of pixel replication sequences are provided. A scale factor is selected. Providing the pixel replication sequences includes: selecting a first pixel of the original image, selecting a scale offset parameter, adding the selected scale factor to the selected scale offset, producing a first sum, and comparing the first sum to a maximum sum. A pixel replication sequence is selected for the desired scale factor. A selected first pixel of the original image is mapped into a first pixel location in the enlarged image. If the first sum is less than the maximum sum, the selected first pixel is also mapped into a second pixel location in the enlarged image.

Abstract: The invention is directed to a method and apparatus for selecting pixels to write to a buffer when creating an enlarged image. The apparatus includes a display pipe for buffering a row of pixels to be rendered in a display space, and a controller for writing display pixels to the display pipe. The controller is adapted for determining which pixels in a row of pixels are non-display pixels so that the controller does not write the non-display pixels to the display pipe. Preferably, the apparatus includes a memory for storing the original image. The method includes the steps of determining which pixels in a row of pixels are non-display pixels; and forwarding the display pixels for rendering in the display space so that the non-display pixels are not forwarded for rendering in the display space.

Abstract: An overlay control circuit and method. In a preferred embodiment of the invention, a graphics controller provides main image data and overlay image data to a display device and includes a memory for storing the main image data and the overlay image data and a logic circuit for producing a signal that, in an active state, indicates that a particular location in the display device is to be represented by the overlay image data. The overlay control circuit fetches the main image data from the memory and is further adapted to respond to a transition in the indicating signal to the active state by halting the fetching.

Abstract: A system and method for continuously tracing transfer rectangles for performing image data transfers includes a display controller with control logic, a rectangle module, and a coordinates module. The rectangle module detects write operations to on-screen data in a video memory, and then updates a primary transfer rectangle during a normal mode to include pixel data from the foregoing write operations. The coordinates module stores the primary transfer rectangle for performing a current transfer operation. The coordinates module enters a pause mode before initiating the current transfer operation, and retains the primary transfer rectangle during the pause mode. The coordinate module also stores a secondary transfer rectangle formed during the pause mode by detecting the foregoing write operations. The controller logic instructs the coordinates module to resume the normal mode after the current transfer operation concludes.

Abstract: A power cut-off protection control circuit and method. A memory pair and a selecting circuit are provided. The memory pair stores data made available at respective storage inputs of first and second storage elements of the pair and provides the stored data at respective storage outputs thereof. The memory pair has a polarity selecting input through which the output of one of the first and second storage elements is caused to correspond to a first control state of the switch and the output of the other of the first and second storage elements is caused to correspond to a second control state of the switch. The selecting circuit has inputs coupled to the respective storage outputs of the memory pair and an output coupled to a control line of the switch for controlling the switch. A selecting line of the selecting circuit selects between the inputs, for selecting one or the other of the storage outputs of the first and second storage elements.

Abstract: A system and method for detecting memory writes to initiate image data transfers includes a display controller device with a write detector module and controller logic. The write detector module detects write operations from a host central-processing unit to on-screen data in a video memory of the display controller. The write detector module responsively sets a transfer flag to indicate that the on-screen data has been modified. The controller logic then detects that the transfer flag has been set by the write detector module. The controller logic may then efficiently initiate a frame transfer operation for transferring the modified on-screen data from the video memory to a display of a host electronic device.

Abstract: A system and method for performing automatic partial transfers of image data includes a display controller with controller logic, a rectangle module, and an automatic transfer module. The rectangle module detects write operations to on-screen data in a video memory, and then updates a transfer rectangle to include written data from the foregoing write operations. The controller logic sets a transfer flag in response to a transfer trigger event in the display controller for initiating an automatic partial transfer operation from the video memory to a display device. The automatic transfer module performs automatic transfer configuration procedures to prepare the display device for the automatic partial transfer operation. The automatic transfer module then automatically transfers rectangle data of the transfer rectangle from the video memory to the display device to complete the automatic partial transfer operation.

Abstract: A system and method for detecting memory location modifications to initiate image data transfers includes a display controller device with a location detector module and controller logic. The location detector module detects register write operations from a host central-processing unit to on-screen registers in a controller registers of the display controller. The on-screen registers define where in a video memory of the display controller the on-screen data is stored. The location detector module responsively sets a transfer flag to indicate that one or more memory locations of the on-screen data have been modified. The controller logic then detects that the transfer flag has been set by the location detector module. The controller logic may then efficiently initiate a frame transfer operation for transferring the appropriate on-screen data from the video memory to a display of a host electronic device.

Abstract: A memory efficient method and apparatus for compression encoding large overlaid camera images. Main image data are combined with overlay image data to form composite image data, and the composite image data are compression encoded. According to one aspect of the invention, the overlay image data are stored in a memory, fetched, up-scaled, and then combined with the main image data to form the composite image data. According to another aspect of the invention, the overlay image data are stored in a memory, fetched, and then combined with main image data streamed from a source of the main image data.

Abstract: A memory efficient method and apparatus for displaying large overlaid camera images. According to one aspect of the invention, overlay image data are stored in a memory, fetched, up-scaled, and then combined with main image data to form composite image data for rendering on a graphics display device. According to another aspect of the invention, the overlay image data are stored in a memory, fetched, and then combined with main image data streamed from a source of the main image data.

Abstract: A method and apparatus for high speed addressing of memory locations within the same page. Generally, a first selected location in the memory space is accessed using at least a first and second part of the address. Then, a first part of the address of a second selected location in the memory space is transmitted. The method and apparatus determine whether at least a second part of the address of the second selected location corresponding to the second part of the address of the first selected location is the same as the second part of the address of the first selected location, and determines the address for the second selected location without transmitting the second part of the address of the second selected location by joining the second part of the address of the first selected location with the first part of the address of the second location on the condition that the second part of the address of the second selected location is the same as the second part of the address of the first selected location.

Abstract: A method and apparatus for high speed addressing of a memory space from a relatively small address space. An N-bit bus interfaces with a memory device having a 2M address memory space, where M is greater than N. The method and apparatus provide for (a) providing at least two registers, (b) receiving one byte of a plurality of N-bit bytes that together define an address in the memory space, (c) incrementing a count as a result of completing step (b), (d) addressing one of the two registers according to the incremented count in step (c), and (e) storing the one byte in the register addressed in step (d).