Patents by Inventor Atri Chatterjee

Atri Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20260093966
    Abstract: A system comprising a pre-compute storage memory comprising a plurality of pre-computed results that correspond to a neural network operation during inferencing or training, wherein the pre-compute storage memory is configured to provide the plurality of pre-computed results as output that is used in determining an activation of a next layer in a neural network; a memory array configured to store a plurality of weight activation sets; an address decoder configured to (i) generate an address in the pre-compute storage memory that matches an input operand, wherein the address corresponds to a weight activation set of the plurality of weight activation sets that matches the input operand and (ii) fetch a pre-computed result of the plurality of pre-compute results from the pre-compute storage memory based on the address.
    Type: Application
    Filed: September 2, 2025
    Publication date: April 2, 2026
    Inventors: Swarup Bhunia, Baibhab Chatterjee, Atri Chatterjee, Habibur Rahaman
  • Publication number: 20260039485
    Abstract: An apparatus comprising a pair of inverters configured in a cross-coupled configuration, wherein an inverter of the pair of inverters comprises a static random-access memory (SRAM) physically unclonable function (PUF) circuit, wherein the SRAM PUF circuit comprises an inverter; and an inverter cell comprising a p-channel metal-oxide-semiconductor (PMOS) transistor, an n-channel metal-oxide-semiconductor (NMOS) transistor, and output node, and a control signal input, wherein: (i) the PMOS transistor comprises (a) a drain terminal that is coupled to an output and (b) a source terminal that is coupled to a supply voltage, (ii) the NMOS transistor comprises a gate terminal that is coupled to a gate of the PMOS transistor that inhibits a path between the supply voltage and ground, and (iii) responsive to a low state provided to the control signal input, the control signal input causes the PMOS transistor to charge the output node to the supply voltage.
    Type: Application
    Filed: July 29, 2025
    Publication date: February 5, 2026
    Inventors: Swarup Bhunia, Atri Chatterjee, Peyman Dehghanzadeh
  • Publication number: 20250384197
    Abstract: A reconfiguration security fabric comprising a reconfigurable logic block (ReCLB) comprising a plurality of lookup tables (LUTs); one or more programmable input/output (PIO) routers comprising a plurality of multiplexers (MUXs) that determine routing of data to or from the ReCLB; a switch box that is configured to route a plurality of outputs from the plurality of LUTs to the one or more PIO routers; and a configuration bitstream that is communicatively coupled to the ReCLB, the one or more PIO routers, and the switch box, wherein functionality of the ReCLB, the one or more PIO routers, and the switch box is altered by shifting the configuration bitstream.
    Type: Application
    Filed: May 30, 2025
    Publication date: December 18, 2025
    Inventors: Swarup Bhunia, Aritra Dasgupta, Atri Chatterjee, Sudipta Paria, Habibur Rahaman
  • Patent number: 9791998
    Abstract: A system, method and computer program product are provided for managing a plurality of applications via a single interface. It is initially identified as to which of a plurality of applications are installed on a computer. A status of each of the applications is then presented via a single graphical user interface.
    Type: Grant
    Filed: December 23, 2014
    Date of Patent: October 17, 2017
    Assignee: McAfee, Inc.
    Inventors: Brent J. Lymer, Atri Chatterjee
  • Patent number: 9177140
    Abstract: A system, method and computer program product are provided for managing a plurality of applications via a single interface. It is initially identified as to which of a plurality of applications are installed on a computer. A status of each of the applications is then presented via a single graphical user interface.
    Type: Grant
    Filed: September 14, 2007
    Date of Patent: November 3, 2015
    Inventors: Brent J. Lymer, Atri Chatterjee
  • Publication number: 20150113421
    Abstract: A system, method and computer program product are provided for managing a plurality of applications via a single interface. It is initially identified as to which of a plurality of applications are installed on a computer. A status of each of the applications is then presented via a single graphical user interface.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 23, 2015
    Inventors: Brent J. Lymer, Atri Chatterjee
  • Publication number: 20150113654
    Abstract: A system, method and computer program product are provided for managing a plurality of applications via a single interface. It is initially identified as to which of a plurality of applications are installed on a computer. A status of each of the applications is then presented via a single graphical user interface.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 23, 2015
    Inventors: Brent J. Lymer, Atri Chatterjee
  • Patent number: 8990723
    Abstract: A system, method and computer program product are provided for managing a plurality of applications via a single interface. It is initially identified as to which of a plurality of applications are installed on a computer. A status of each of the applications is then presented via a single graphical user interface.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: March 24, 2015
    Assignee: McAfee, Inc.
    Inventors: Brent J. Lymer, Atri Chatterjee