Patents by Inventor Atri Rudra

Atri Rudra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7925604
    Abstract: The embodiments of the invention provide a method of ordering an intersecting of a group of lists into a left-deep AND-tree. The method begins by performing a first selecting process including selecting a top list, corresponding to a top leaf of the left-deep AND-tree, from the group of lists to leave remaining lists of the group of lists. The top list can be the smallest list of the group of lists. The method can also select a pair of lists from the group of lists, such that the pair of lists has the smallest intersection size relative to other pairs of lists of the group of lists. Next, the method estimates intersections of the remaining lists with the top list by estimating an amount of intersection between the remaining lists and the top list. This involves sampling a portion of the remaining lists. The method also includes identifying larger list pairs having smaller intersections sizes when compared to smaller list pairs having larger intersections sizes.
    Type: Grant
    Filed: October 25, 2007
    Date of Patent: April 12, 2011
    Assignee: International Business Machines Corporation
    Inventors: Robert Krauthgamer, Aranyak Mehta, Vijayshankar Raman, Atri Rudra
  • Publication number: 20090113309
    Abstract: The embodiments of the invention provide a method of intersecting a group of lists. The method begins by performing a first selecting process including selecting a top list from the group of lists to leave remaining lists. The top list can be the smallest list of the group of lists. The method can also select a pair of lists from the group of lists, such that the pair of lists has the smallest intersection size relative to other pairs of lists of the group of lists. Next, the method estimates intersections of the remaining lists with the top list by estimating an amount of intersection between the remaining lists and the top list. This involves sampling a portion of the remaining lists. The method also includes identifying larger list pairs having smaller intersections sizes when compared to smaller list pairs having larger intersections sizes.
    Type: Application
    Filed: October 25, 2007
    Publication date: April 30, 2009
    Inventors: Robert Krauthgamer, Aranyak Mehta, Vijayshankar Raman, Atri Rudra
  • Patent number: 6766344
    Abstract: Efficient parallel processing of algorithms involving Galois Field arithmetic use data slicing techniques to execute arithmetic operations on a computing hardware having SIMD (single-instruction, multiple-data) architectures. A W-bit wide word computer capable of operating on one or more sets of k-bit operands executes Galois Field arithmetic by mapping arithmetic operations of Galois Field GF(2n) to corresponding operations in subfields lower order (m<n), which one selected on the basis of an appropriate cost function. These corresponding operations are able to be simultaneously executed on the W-bit wide computer such that the results of the arithmetic operations in Galois Field GF(2n) are obtained in k/W as many cycles of the W-bit computer compared with execution of the corresponding operations on a k-bit computer.
    Type: Grant
    Filed: May 8, 2001
    Date of Patent: July 20, 2004
    Assignee: International Business Machines Corporation
    Inventors: Pradeep K Dubey, Charanjit Jutla, Josyula R Rao, Pankaj Rohatgi, Atri Rudra, Vijay Kumar
  • Publication number: 20030055858
    Abstract: Efficient parallel processing of algorithms involving Galois Field arithmetic use data slicing techniques to execute arithmetic operations on a computing hardware having SIMD architectures. A W-bit wide word computer capable of operating on one or more sets of k-bit operands executes Galois Field arithmetic by mapping arithmetic operations of Galois Field GF(2n) to corresponding operations in subfields lower order (m<n), which one selected on the basis of an appropriate cost function. These corresponding operations are able to be simultaneously executed on the W-bit wide computer such that the results of the arithmetic operations in Galois Field GF(2n) are obtained in k/W as many cycles of the W-bit computer compared with execution of the corresponding operations on a k-bit computer.
    Type: Application
    Filed: May 8, 2001
    Publication date: March 20, 2003
    Applicant: International Business Machines Corporation
    Inventors: Pradeep K. Dubey, Charanjit Jutla, Josyula R. Rao, Pankaj Rohatgi, Atri Rudra, Vijay Kumar