Abstract: In a power supply system, reducing influence of a noise etc., optimal electric power is supplied corresponding to power consumption of a receiving side load, and power consumption is decreased greatly. When a potential difference detector 12 detects that a power supply voltage of the receiving side load is decreased lower than a lower limit voltage threshold or increased higher than an upper limit voltage threshold, a burst interval setting unit sets up a burst signal of a pulse width corresponding to the detection result. A burst signal generator generates a burst signal based on the setup, and excites a control primary inductor. A burst signal detector generates a pulse signal in response to electromotive force of a control secondary inductor.

Abstract: The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

Abstract: The present invention provides a semiconductor device in which an adjustable range of a resistance value of a variable resistance circuit is large. The semiconductor device has an output buffer including a plurality of sets of resistance elements and a plurality of sets of transistors, a plurality of replica circuits, and a plurality of sets of operational amplifiers, and drain currents of the plurality of sets of transistors are adjusted so that output impedances of the output buffer become predetermined values. Therefore, even in the case where the resistance values of the resistance elements largely fluctuate due to fluctuations in manufacture process and the like, the output impedances can be set to predetermined values.

Abstract: A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Abstract: In a power supply system, reducing influence of a noise etc., optimal electric power is supplied corresponding to power consumption of a receiving side load, and power consumption is decreased greatly. When a potential difference detector 12 detects that a power supply voltage of the receiving side load is decreased lower than a lower limit voltage threshold or increased higher than an upper limit voltage threshold, a burst interval setting unit sets up a burst signal of a pulse width corresponding to the detection result. A burst signal generator generates a burst signal based on the setup, and excites a control primary inductor. A burst signal detector generates a pulse signal in response to electromotive force of a control secondary inductor.

Abstract: A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Abstract: A phase comparison circuit detects a phase difference between a data signal and the output from a variable delay circuit. A Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of the variable delay circuit exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by the phase delay circuit, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.

Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.

Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.

Abstract: PD detects a phase difference between DATA and VDL output from VDL. Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of VDL exceeds one period of a clock during synchronization of the output clock with the data signal while the control code is changed in accordance with the detection result by PD, a control code corresponding to a delay equal to one period of the output clock is added or subtracted to/from the control code at a time. Therefore, even if there is a difference in frequency between a data signal and a clock, it becomes possible to synchronize the data signal and the clock with application of the same clock phase.

Abstract: The present invention provides an equalizer and a semiconductor device, that can suppress a decrease in S/N ratio of a reception signal, can facilitate a disconnection test by a direct current signal, and are excellent in reproducibility of a transmission signal. A low-pass filter receives a reception signal supplied from a reception end to output a signal obtained by removing a high frequency component from the reception signal. A subtraction unit subtracts an output signal from the low-pass filter from the reception signal. An addition unit adds the reception signal from the reception end to an output signal from the subtraction unit. Thus, an output signal from the addition unit has a frequency characteristic of emphasizing the high frequency component. Then, an amplifier amplifies the output signal from the addition unit to transmit it to an output end.

Abstract: Provided is a disconnection and short detecting circuit capable of detecting disconnection and short of a signal line transmitting a differential clock signal. A differential buffer part DB1 has a first comparator to compare a non-inverting clock signal inputted from a PADI and an inverting clock signal inputted from a PADR; a second comparator to compare a non-inverting clock signal and a reference potential Vref; and a third comparator to compare an inverting clock signal and the reference potential Vref. Their respective outputs are defined as Y, YI and YR, respectively. If the signal line of either a non-inverting clock signal or an inverting clock signal is disconnected, or short-circuited to a grounding potential VSS of a logical value Low, the logical values outputted from the second and the third comparators are equal for a long period of time in one cycle of the non-inverting clock signal or the inverting clock signal.

Abstract: Assuming that clocks in an A clock driver (102), a B clock driver (103) and a CMOS buffer circuit (119) have delay values Ta, Tb and Td, respectively, a delay value Ta?Td is stored in a register circuit (117) when terminals “0” of selector circuits (114, 115, 116) are selected, and a delay value Ta?Td?Tb is stored in a register circuit (118) when the terminals “0” are switched to “1”. Thus, determining a delay value at the CMOS buffer circuit (119) allows a phase difference between the A clock driver (102) and B clock driver (103) to be determined.

Abstract: There are provided a lock detector that does not output a lock detecting signal of incorrect content even when approaching phase synchronization, when an input signal stops suddenly, or when a phase difference becomes zero momentarily in the progress that an output signal is synchronized with an input signal, as well as a PLL circuit including this lock detector. Specifically, a PLL circuit includes a lock detector (20) which comprises a reset signal output part (6, 7, 22 to 24) that outputs a reset signal (Pe) upon a phase difference between an input signal (f1) and a feedback signal (f2); and a D-FF circuit (8) that does not output a lock detecting signal (SL) upon receipt of the reset signal. The feedback signal (f2) is inputted to an NAND circuit (23) such that the reset signal is also based on the signal change of the feedback signal (f2). Further, a counter (21) performing output when the input signal (f1) reaches N-cycle is used for the clock of the D-FF circuit (8).

Abstract: Assuming that clocks in an A clock driver (102), a B clock driver (103) and a CMOS buffer circuit (119) have delay values Ta, Tb and Td, respectively, a delay value Ta−Td is stored in a register circuit (117) when terminals “0” of selector circuits (114, 115, 116) are selected, and a delay value Ta−Td−Tb is stored in a register circuit (118) when the terminals “0” are switched to “1”. Thus, determining a delay value at the CMOS buffer circuit (119) allows a phase difference between the A clock driver (102) and B clock driver (103) to be determined.

Abstract: There are provided a lock detector that does not output a lock detecting signal of incorrect content even when approaching phase synchronization, when an input signal stops suddenly, or when a phase difference becomes zero momentarily in the progress that an output signal is synchronized with an input signal, as well as a PLL circuit including this lock detector. Specifically, a PLL circuit includes a lock detector (20) which comprises a reset signal output part (6, 7, 22 to 24) that outputs a reset signal (Pe) upon a phase difference between an input signal (f1) and a feedback signal (f2); and a D-FF circuit (8) that does not output a lock detecting signal (SL) upon receipt of the reset signal. The feedback signal (f2) is inputted to an NAND circuit (23) such that the reset signal is also based on the signal change of the feedback signal (f2). Further, a counter (21) performing output when the input signal (f1) reaches N-cycle is used for the clock of the D-FF circuit (8).

Abstract: A circuit for suppressing period jitter of the clock output of a ring oscillator caused by supply voltage fluctuations. The ring oscillator includes n identical current controlled delay circuits 26.1-n connected in a ring, and a replica circuit 36 identical to the current controlled delay circuit. The replica circuit 36 receives a constant input voltage so that its output is always at a high level. A differential amplifier 35 receiving a reference potential Vref is connected in a negative feedback circuit with replica circuit 36, so that the output of the replica circuit 36 is held equal to the reference potential Vref. An output of the negative feedback circuit is also applied to each of the current controlled delay circuits 26.1-n, so that their high level outputs are held equal to the reference potential Vref.