Abstract: In a transmission rate converting device, a write data serial-to-parallel converter converts data input to the device to parallel data. A frame pattern generator adds dummy data to the parallel data such that each multiframe forms a multiframe pattern subjected to conversion. The parallel data with the dummy data are written to a RAM (Random Access Memory) included in a FIFO (First-In First-Out) memory via a write port and then read thereoutof. A read data parallel-to-serial converter converts the parallel data read out of the RAM to serial data. A clock comparison and control controls a write clock generator and a read clock generator such that the number of frames stored in the RAM remains in a predetermined range.