Patents by Inventor Atsuhiro Ando
Atsuhiro Ando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230068256Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate. The present disclosure can be applied to, for example, the image pickup device, and the like.Type: ApplicationFiled: November 7, 2022Publication date: March 2, 2023Applicant: SONY GROUP CORPORATIONInventors: Hiroaki ISHIWATA, Harumi TANAKA, Atsuhiro ANDO
-
Patent number: 11532651Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.Type: GrantFiled: May 5, 2021Date of Patent: December 20, 2022Assignee: SONY GROUP CORPORATIONInventors: Hiroaki Ishiwata, Harumi Tanaka, Atsuhiro Ando
-
Publication number: 20210257397Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.Type: ApplicationFiled: May 5, 2021Publication date: August 19, 2021Applicant: SONY GROUP CORPORATIONInventors: Hiroaki ISHIWATA, Harumi TANAKA, Atsuhiro ANDO
-
Patent number: 11031420Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.Type: GrantFiled: November 19, 2019Date of Patent: June 8, 2021Assignee: SONY CORPORATIONInventors: Hiroaki Ishiwata, Harumi Tanaka, Atsuhiro Ando
-
Patent number: 10748947Abstract: The present disclosure relates to an imaging device, a manufacturing method, and an electronic apparatus. An imaging device includes: a sensor substrate with an effective pixel area; a transparent sealing member that seals a surface of the sensor substrate; a sealing resin that bonds the sensor substrate and the sealing member; and a reinforcing resin that bonds the sensor substrate and the sealing member. A product of adhesive strength per unit area of the sealing resin and the reinforcing resin in the outer peripheral region and an area of a part bonded in the outer peripheral region is set to be larger than a product of adhesive strength per unit area of the sealing resin in the effective pixel area and an area of a part bonded in the effective pixel area. The present technology can be applied to, for example, a CMOS image sensor of WCSP.Type: GrantFiled: July 25, 2017Date of Patent: August 18, 2020Assignee: Sony Semiconductor Solutions CorporationInventors: Yoshiaki Masuda, Atsuhiro Ando, Norihiro Kubo, Chihiro Arai, Sotetsu Saito, Masahiro Tada, Shinji Miyazawa
-
Publication number: 20200161347Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.Type: ApplicationFiled: November 19, 2019Publication date: May 21, 2020Applicant: SONY CORPORATIONInventors: Hiroaki ISHIWATA, Harumi TANAKA, Atsuhiro ANDO
-
Patent number: 10529752Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.Type: GrantFiled: March 10, 2017Date of Patent: January 7, 2020Assignee: Sony CorporationInventors: Hiroaki Ishiwata, Harumi Tanaka, Atsuhiro Ando
-
Publication number: 20190172863Abstract: The present disclosure relates to an imaging device, a manufacturing method, and an electronic apparatus—An imaging device includes: a sensor substrate with an effective pixel area; a transparent sealing member that seals a surface of the sensor substrate; a sealing resin that bonds the sensor substrate and the sealing member; and a reinforcing resin that bonds the sensor substrate and the sealing member. A product of adhesive strength per unit area of the sealing resin and the reinforcing resin in the outer peripheral region and an area of a part bonded in the outer peripheral region is set to be larger than a product of adhesive strength per unit area of the sealing resin in the effective pixel area and an area of a part bonded in the effective pixel area. The present technology can be applied to, for example, a CMOS image sensor of WCSP.Type: ApplicationFiled: July 25, 2017Publication date: June 6, 2019Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Yoshiaki MASUDA, Atsuhiro ANDO, Norihiro KUBO, Chihiro ARAI, Sotetsu SAITO, Masahiro TADA, Shinji MIYAZAWA
-
Patent number: 10236311Abstract: The present technology relates to a solid-state imaging element and an electronic device capable of improving image quality of the solid-state imaging element. The solid-state imaging element includes a photoelectric conversion unit adapted to photoelectrically convert incident light incident from a predetermined incident surface. Also, the solid-state imaging element includes a wire arranged on a bottom surface side that is an opposite surface of the incident surface of the photoelectric conversion unit, and formed with a protruding pattern on a surface facing the photoelectric conversion unit. The present technology can be applied to, for example, a solid-state imaging element such as a CMOS image sensor, and an electronic device including the solid-state imaging element.Type: GrantFiled: October 7, 2015Date of Patent: March 19, 2019Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Ryoji Suzuki, Hitoshi Moriya, Atsuhiro Ando, Atsushi Masagaki
-
Publication number: 20190057989Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.Type: ApplicationFiled: March 10, 2017Publication date: February 21, 2019Applicant: SONY CORPORATIONInventors: Hiroaki ISHIWATA, Harumi TANAKA, Atsuhiro ANDO
-
Publication number: 20170229503Abstract: The present technology relates to a solid-state imaging element and an electronic device capable of improving image quality of the solid-state imaging element. The solid-state imaging element includes a photoelectric conversion unit adapted to photoelectrically convert incident light incident from a predetermined incident surface. Also, the solid-state imaging element includes a wire arranged on a bottom surface side that is an opposite surface of the incident surface of the photoelectric conversion unit, and formed with a protruding pattern on a surface facing the photoelectric conversion unit. The present technology can be applied to, for example, a solid-state imaging element such as a CMOS image sensor, and an electronic device including the solid-state imaging element.Type: ApplicationFiled: October 7, 2015Publication date: August 10, 2017Inventors: RYOJI SUZUKI, HITOSHI MORIYA, ATSUHIRO ANDO, ATSUSHI MASAGAKI
-
Patent number: 8736727Abstract: A solid-state imaging device includes a photoelectric conversion portion, a charge-receiving portion to which charges are transferred from the photoelectric conversion portion, and a light control film having a reverse tapered opening over the photoelectric conversion portion to reduce the intensity of diffracted light diffusing to regions other than the photoelectric conversion portion.Type: GrantFiled: March 25, 2011Date of Patent: May 27, 2014Assignee: Sony CorporationInventor: Atsuhiro Ando
-
Publication number: 20110242376Abstract: A solid-state imaging device includes a photoelectric conversion portion, a charge-receiving portion to which charges are transferred from the photoelectric conversion portion, and a light control film having a reverse tapered opening over the photoelectric conversion portion to reduce the intensity of diffracted light diffusing to regions other than the photoelectric conversion portion.Type: ApplicationFiled: March 25, 2011Publication date: October 6, 2011Applicant: SONY CORPORATIONInventor: Atsuhiro Ando
-
Patent number: 8012840Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.Type: GrantFiled: May 27, 2009Date of Patent: September 6, 2011Assignee: Sony CorporationInventor: Atsuhiro Ando
-
Publication number: 20090233411Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.Type: ApplicationFiled: May 27, 2009Publication date: September 17, 2009Applicant: SONY CORPORATIONInventor: Atsuhiro Ando
-
Patent number: 7557396Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.Type: GrantFiled: February 21, 2006Date of Patent: July 7, 2009Assignee: Sony CorporationInventor: Atsuhiro Ando
-
Publication number: 20070298615Abstract: A pattern forming method is provided. The pattern forming method includes a first step of forming a resist pattern including a lactone group-containing skeleton above an etched layer provided on a substrate; a second step of performing plasma processing using a hydrogen-containing gas to lower a glass transition temperature or a softening point of the resist pattern; and a third step of transferring the resist pattern after the plasma processing to the etched layer by etching, and forming the pattern of the etched layer.Type: ApplicationFiled: January 30, 2007Publication date: December 27, 2007Inventors: Nobuyuki Matsuzawa, Atsuhiro Ando, Eriko Matsui, Yuko Yamaguchi, Katsuhisa Kugimiya, Tetsuya Tatsumi, Salam Kazi, Takeshi Iwai, Makiko Irie
-
Publication number: 20060192232Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.Type: ApplicationFiled: February 21, 2006Publication date: August 31, 2006Inventor: Atsuhiro Ando