Patents by Inventor Atsuhiro Ando

Atsuhiro Ando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240313030
    Abstract: A first light-receiving element of an embodiment of the disclosure includes: a semiconductor substrate including a photoelectric conversion region; a first first electrically-conductive region provided at a first surface interface of the semiconductor substrate and coupled to a first electrode; a second first electrically-conductive region provided around the first first electrically-conductive region and coupled to a second electrode, at the first surface interface; a third first electrically-conductive region in an electrically floating state provided around the second first electrically-conductive region, at the first surface interface; a first second electrically-conductive region having a different electrically-conductive type between the first first electrically-conductive region and the second first electrically-conductive region, at the first surface interface; and a fourth first electrically-conductive region provided at least between the first first electrically conductive region and the first secon
    Type: Application
    Filed: March 25, 2022
    Publication date: September 19, 2024
    Applicants: SONY SEMICONDUCTOR SOLUTIONS CORPORATION, RIKEN
    Inventors: Takahiro KAWAMURA, Hiroki TOJINBARA, Takaki HATSUI, Shinichi YOSHIDA, Keiichi NAKAZAWA, Hikaru IWATA, Kazunobu OTA, Takuya MARUYAMA, Hiroaki ISHIWATA, Chihiro ARAI, Atsuhiro ANDO, Toru SHIRAKATA, Hisahiro ANSAI, Satoe MIYATA, Ryu KAMIBABA, Yusuke UESAKA, Yukari TAKEYA
  • Publication number: 20240290814
    Abstract: A first light-receiving device of an embodiment of the disclosure includes: a first semiconductor substrate having first and second surfaces opposed to each other, receiving application of a first potential, and including light-receiving elements arranged two-dimensionally in matrix; a second semiconductor substrate having third and fourth surfaces opposed to each other, with the first surface and the third surface being disposed to be opposed to each other, receiving application of a second potential lower than the first potential, and including a logic circuit that processes a light-receiving signal based on electric charge outputted from the plurality of light-receiving elements; and an interlayer insulating layer provided between the first and second semiconductor substrates, in which the second semiconductor substrate has a side surface recessed more inward than a side surface of the first semiconductor substrate, and the side surface of the second semiconductor substrate is coated with a protective film
    Type: Application
    Filed: March 16, 2022
    Publication date: August 29, 2024
    Inventors: TORU SHIRAKATA, HIKARU IWATA, MASANARI YAMAGUCHI, KAZUNOBU OTA, ATSUHIRO ANDO, DAIKI SAKAI, AKIRA MAEHARA
  • Publication number: 20240194701
    Abstract: A light-receiving element according to an embodiment of the present disclosure includes: a semiconductor substrate including a photoelectric conversion region; a first first electrically-conductive region provided at an interface of a first surface of the semiconductor substrate and coupled to a first electrode; a second first electrically-conductive region provided at the interface of the first surface and around the first first electrically-conductive region and coupled to a second electrode; a third first electrically-conductive region provided at the interface of the first surface and around the second first electrically-conductive region and being in an electrically floating state; and an electrically-conductive film provided above the first surface at least between the first first electrically-conductive region and the second first electrically-conductive region.
    Type: Application
    Filed: March 25, 2022
    Publication date: June 13, 2024
    Applicants: SONY SEMICONDUCTOR SOLUTIONS CORPORATION, RIKEN
    Inventors: Takaki HATSUI, Takahiro KAWAMURA, Hiroki TOJINBARA, Kazunobu OTA, Toru SHIRAKATA, Hikaru IWATA, Atsuhiro ANDO
  • Patent number: 11984462
    Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate. The present disclosure can be applied to, for example, the image pickup device, and the like.
    Type: Grant
    Filed: November 7, 2022
    Date of Patent: May 14, 2024
    Assignee: Sony Group Corporation
    Inventors: Hiroaki Ishiwata, Harumi Tanaka, Atsuhiro Ando
  • Publication number: 20230068256
    Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate. The present disclosure can be applied to, for example, the image pickup device, and the like.
    Type: Application
    Filed: November 7, 2022
    Publication date: March 2, 2023
    Applicant: SONY GROUP CORPORATION
    Inventors: Hiroaki ISHIWATA, Harumi TANAKA, Atsuhiro ANDO
  • Patent number: 11532651
    Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: December 20, 2022
    Assignee: SONY GROUP CORPORATION
    Inventors: Hiroaki Ishiwata, Harumi Tanaka, Atsuhiro Ando
  • Publication number: 20210257397
    Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.
    Type: Application
    Filed: May 5, 2021
    Publication date: August 19, 2021
    Applicant: SONY GROUP CORPORATION
    Inventors: Hiroaki ISHIWATA, Harumi TANAKA, Atsuhiro ANDO
  • Patent number: 11031420
    Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: June 8, 2021
    Assignee: SONY CORPORATION
    Inventors: Hiroaki Ishiwata, Harumi Tanaka, Atsuhiro Ando
  • Patent number: 10748947
    Abstract: The present disclosure relates to an imaging device, a manufacturing method, and an electronic apparatus. An imaging device includes: a sensor substrate with an effective pixel area; a transparent sealing member that seals a surface of the sensor substrate; a sealing resin that bonds the sensor substrate and the sealing member; and a reinforcing resin that bonds the sensor substrate and the sealing member. A product of adhesive strength per unit area of the sealing resin and the reinforcing resin in the outer peripheral region and an area of a part bonded in the outer peripheral region is set to be larger than a product of adhesive strength per unit area of the sealing resin in the effective pixel area and an area of a part bonded in the effective pixel area. The present technology can be applied to, for example, a CMOS image sensor of WCSP.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: August 18, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Yoshiaki Masuda, Atsuhiro Ando, Norihiro Kubo, Chihiro Arai, Sotetsu Saito, Masahiro Tada, Shinji Miyazawa
  • Publication number: 20200161347
    Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.
    Type: Application
    Filed: November 19, 2019
    Publication date: May 21, 2020
    Applicant: SONY CORPORATION
    Inventors: Hiroaki ISHIWATA, Harumi TANAKA, Atsuhiro ANDO
  • Patent number: 10529752
    Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: January 7, 2020
    Assignee: Sony Corporation
    Inventors: Hiroaki Ishiwata, Harumi Tanaka, Atsuhiro Ando
  • Publication number: 20190172863
    Abstract: The present disclosure relates to an imaging device, a manufacturing method, and an electronic apparatus—An imaging device includes: a sensor substrate with an effective pixel area; a transparent sealing member that seals a surface of the sensor substrate; a sealing resin that bonds the sensor substrate and the sealing member; and a reinforcing resin that bonds the sensor substrate and the sealing member. A product of adhesive strength per unit area of the sealing resin and the reinforcing resin in the outer peripheral region and an area of a part bonded in the outer peripheral region is set to be larger than a product of adhesive strength per unit area of the sealing resin in the effective pixel area and an area of a part bonded in the effective pixel area. The present technology can be applied to, for example, a CMOS image sensor of WCSP.
    Type: Application
    Filed: July 25, 2017
    Publication date: June 6, 2019
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshiaki MASUDA, Atsuhiro ANDO, Norihiro KUBO, Chihiro ARAI, Sotetsu SAITO, Masahiro TADA, Shinji MIYAZAWA
  • Patent number: 10236311
    Abstract: The present technology relates to a solid-state imaging element and an electronic device capable of improving image quality of the solid-state imaging element. The solid-state imaging element includes a photoelectric conversion unit adapted to photoelectrically convert incident light incident from a predetermined incident surface. Also, the solid-state imaging element includes a wire arranged on a bottom surface side that is an opposite surface of the incident surface of the photoelectric conversion unit, and formed with a protruding pattern on a surface facing the photoelectric conversion unit. The present technology can be applied to, for example, a solid-state imaging element such as a CMOS image sensor, and an electronic device including the solid-state imaging element.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: March 19, 2019
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Ryoji Suzuki, Hitoshi Moriya, Atsuhiro Ando, Atsushi Masagaki
  • Publication number: 20190057989
    Abstract: The present disclosure relates to an image pickup device and an electronic apparatus that enable warping of a substrate to be suppressed. A first structural body including a pixel array unit is layered with a second structural body including an input/output circuit unit and outputting a pixel signal output from the pixel to the outside of the device, and a signal processing circuit; and a signal output external terminal and a signal input external terminal are arranged below the pixel array unit, the signal output external terminal being connected to the outside via a first through-via penetrating through a semiconductor substrate in the second structural body, the signal input external terminal being connected to the outside via a second through-via connected to an input circuit unit and penetrating through the semiconductor substrate.
    Type: Application
    Filed: March 10, 2017
    Publication date: February 21, 2019
    Applicant: SONY CORPORATION
    Inventors: Hiroaki ISHIWATA, Harumi TANAKA, Atsuhiro ANDO
  • Publication number: 20170229503
    Abstract: The present technology relates to a solid-state imaging element and an electronic device capable of improving image quality of the solid-state imaging element. The solid-state imaging element includes a photoelectric conversion unit adapted to photoelectrically convert incident light incident from a predetermined incident surface. Also, the solid-state imaging element includes a wire arranged on a bottom surface side that is an opposite surface of the incident surface of the photoelectric conversion unit, and formed with a protruding pattern on a surface facing the photoelectric conversion unit. The present technology can be applied to, for example, a solid-state imaging element such as a CMOS image sensor, and an electronic device including the solid-state imaging element.
    Type: Application
    Filed: October 7, 2015
    Publication date: August 10, 2017
    Inventors: RYOJI SUZUKI, HITOSHI MORIYA, ATSUHIRO ANDO, ATSUSHI MASAGAKI
  • Patent number: 8736727
    Abstract: A solid-state imaging device includes a photoelectric conversion portion, a charge-receiving portion to which charges are transferred from the photoelectric conversion portion, and a light control film having a reverse tapered opening over the photoelectric conversion portion to reduce the intensity of diffracted light diffusing to regions other than the photoelectric conversion portion.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: May 27, 2014
    Assignee: Sony Corporation
    Inventor: Atsuhiro Ando
  • Publication number: 20110242376
    Abstract: A solid-state imaging device includes a photoelectric conversion portion, a charge-receiving portion to which charges are transferred from the photoelectric conversion portion, and a light control film having a reverse tapered opening over the photoelectric conversion portion to reduce the intensity of diffracted light diffusing to regions other than the photoelectric conversion portion.
    Type: Application
    Filed: March 25, 2011
    Publication date: October 6, 2011
    Applicant: SONY CORPORATION
    Inventor: Atsuhiro Ando
  • Patent number: 8012840
    Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: September 6, 2011
    Assignee: Sony Corporation
    Inventor: Atsuhiro Ando
  • Publication number: 20090233411
    Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.
    Type: Application
    Filed: May 27, 2009
    Publication date: September 17, 2009
    Applicant: SONY CORPORATION
    Inventor: Atsuhiro Ando
  • Patent number: 7557396
    Abstract: A semiconductor device includes a side wall spacer formed on the side surface of a gate electrode formed on the upper side of a semiconductor substrate with a gate insulation film therebetween, extension regions built up on the semiconductor substrate, and source/drain regions formed on the extension regions, wherein a first epitaxial layer is formed so as to fill up portions, cut out at the time of forming the side wall spacer, of the semiconductor substrate, and the extension regions are formed on the first epitaxial layer from a second epitaxial layer of a conduction type opposite to that of the first epitaxial layer.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: July 7, 2009
    Assignee: Sony Corporation
    Inventor: Atsuhiro Ando