Abstract: An image processing device according to the present technology includes: a foreground-background classification unit configured to classify an input image into a foreground image portion which is a portion in which a subject in a foreground is captured and a background image portion which is a portion in which a subject in a background farther than the foreground image portion is captured; a foreground correction unit configured to correct the foreground image portion; and an inconsistency correction unit configured to correct an inconsistent portion caused by the correction of the foreground image portion by the foreground correction unit.

Abstract: The present invention provides an X-ray CT apparatus capable of obtaining a high-quality X-ray CT image by suppressing occurrence of an artifact. The X-ray CT apparatus including an X-ray imaging system including an X-ray irradiation unit and an X-ray detector, a rotating stage disposed between the X-ray irradiation unit and the X-ray detector, a rotation mechanism configured to relatively rotate the X-ray imaging system and the rotating stage about a rotation axis orthogonal to an optical axis of an X-ray that runs from the X-ray irradiation unit to the X-ray detector, and a load mechanism which is set on the stage and applies test force to a test piece includes an angle changing mechanism that tilts a bending tester to change the direction of the test force applied to the test piece by the bending tester from a direction orthogonal to the optical axis of the X-ray.

Abstract: An electromechanical transformation device for an ultrasonic flow meter comprises an alkaline niobate piezoelectric ceramic composition and a rigid body adhered onto the major surface of the ceramic composition. The ceramic composition is made of crystal structures such as orthorhombic crystals formed at the side where the temperature is lower than the orthorhombic-to-tetragonal phase transition temperature, tetragonal crystals formed at the side where temperature is higher that the orthorhombic-to-tetragonal phase transition temperature as well as at the side where the temperature is lower than the tetragonal-to-cubic phase transition temperature, and the cubic crystals formed at the side where the temperature is higher than the tetragonal-to-cubic phase temperature. Young's modulus of the rigid is 60 GPa or more. The volume percent of the ceramic composition existing within a range where the distance from the adhesion point of the piezoelectric ceramic composition and the rigid body is 40% or more.

Abstract: An electromechanical transformation device for an ultrasonic flow meter comprises an alkaline niobate piezoelectric ceramic composition and a rigid body adhered onto the major surface of the ceramic composition. The ceramic composition is made of crystal structures such as orthorhombic crystals formed at the side where the temperature is lower than the orthorhombic-to-tetragonal phase transition temperature, tetragonal crystals formed at the side where temperature is higher that the orthorhombic-to-tetragonal phase transition temperature as well as at the side where the temperature is lower than the tetragonal-to-cubic phase transition temperature, and the cubic crystals formed at the side where the temperature is higher than the tetragonal-to-cubic phase temperature. Young's modulus of the rigid is 60 GPa or more. THe volume percent of the ceramic composition existing within a range where the distance from the adhesion point of the piezoelectric ceramic composition and the rigid body is 40% or more.

Abstract: This invention provides for a piezoelectric ceramic composition having a lead-free alkaline niobate piezoelectric ceramic composition with a favorable piezoelectric property. This invention refers to a piezoelectric ceramic composition 10 that is described as composition formula {Lix(K1-yNay)1-x}(Nb1-zSbz)O3 including the additives of the metallic elements Bi and Fe within the range of the following relational expressions: 0.03?x?0.045; 0.5?y?0.58; 0.03?z?0.045; and 0.006?v?w?0.010 whereof v is the additive amount of Bi (molar ratio), and w is the additive amount of Fe (molar ratio).

Abstract: This invention provides for a piezoelectric ceramic composition having a lead-free alkaline niobate piezoelectric ceramic composition with a favorable piezoelectric property. This invention refers to a piezoelectric ceramic composition 10 that is described as composition formula {Lix(K1-yNay)1-x}(Nb1-zSbz)O3 including the additives of the metallic elements Bi and Fe within the range of the following relational expressions: 0.03?x?0.045; 0.5?y?0.58; 0.03?z?0.045; and 0.006?v?w?0.010 whereof v is the additive amount of Bi (molar ratio), and w is the additive amount of Fe (molar ratio).

Abstract: An electromechanical transformation device comprises an alkaline niobate piezoelectric ceramic composition and a rigid body adhered onto the major surface of the piezoelectric ceramic composition. The piezoelectric ceramic composition is made of crystal structures such as orthorhombic crystals formed at the side where the temperature is lower than the orthorhombic-to-tetragonal phase transition temperature, tetragonal crystals formed at the side where the temperature is higher than the orthorhombic-to-tetragonal phase transition temperature as well as at the side where the temperature is lower than the tetragonal-to-cubic phase transition temperature, and the cubic crystals formed at the side where the temperature is higher than the tetragonal-to-cubic phase transition temperature.

Abstract: An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement.

Abstract: An eye-opening margin measurement method for a high-speed serial data reception circuit which uses a circuit for eye-opening margin measurement involving operation of a clock data recovery circuit without fixing the clock phase. In this method, an error acceleration test can also be made on received data by giving an offset pulse signal to phase information to add a jitter component. The method uses a semiconductor integrated circuit device which includes a serializer/deserializer circuit (SerDes) for receiving serial data and a reference serializer/deserializer circuit (Ref_SerDes) for receiving an accompanying clock signal. The SerDes circuit converts received serial data into parallel data through a recovery clock whose phase is controlled using phase control signal P_CS generated by the Ref_SerDes circuit. An offset pulse signal Offset_Pulse from the pulse-forming circuit is applied to the phase control signal P_CS to make eye-opening margin measurement.

Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.

Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.

Abstract: A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance control circuit includes an impedance comparator which is formed equivalently to the resistive element and the plurality of sets of circuits, and which performs an impedance comparison with each of a plurality of replica circuits to form an up signal that increases the impedance and a down signal that decreases the impedance. Counters are provided adjacent to the individuals of the plurality of sets of circuits to thereby generate the impedance codes in response to the up signal and the down signal.

Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.

Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.

Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.

Abstract: The present invention provides a semiconductor integrated circuit that can perform impedance control and slew rate control independently of each other and simplify the structure of a control circuit. An output circuit comprising plural output MOSFETs connected in parallel is used, from among the plural output MOSFETs, the number of output MOSFETS to be turned on is selected by a first control means to control output impedance, and slew rate is controlled by a second control means controlling a drive signal of the output MOSFETs to be turned on.

Abstract: A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance control circuit includes an impedance comparator which is formed equivalently to the resistive element and the plurality of sets of circuits, and which performs an impedance comparison with each of a plurality of replica circuits to form an up signal that increases the impedance and a down signal that decreases the impedance. Counters are provided adjacent to the individuals of the plurality of sets of circuits to thereby generate the impedance codes in response to the up signal and the down signal.

Abstract: A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance control circuit includes an impedance comparator which is formed equivalently to the resistive element and the plurality of sets of circuits, and which performs an impedance comparison with each of a plurality of replica circuits to form an up signal that increases the impedance and a down signal that decreases the impedance. Counters are provided adjacent to the individuals of the plurality of sets of circuits to thereby generate the impedance codes in response to the up signal and the down signal.

Abstract: A plurality of sets of circuits are provided, each of which generates an impedance code through the use of an impedance control circuit in association with a resistive element connected to an external terminal, and each of which varies the impedance in accordance with such an impedance code. The impedance control circuit includes an impedance comparator which is formed equivalently to the resistive element and the plurality of sets of circuits, and which performs an impedance comparison with each of a plurality of replica circuits to form an up signal that increases the impedance and a down signal that decreases the impedance. Counters are provided adjacent to the individuals of the plurality of sets of circuits to thereby generate the impedance codes in response to the up signal and the down signal.

Abstract: A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.