Abstract: A semiconductor device includes a first MIS transistor formed on a first active region, and a second MIS transistor formed on a second active region. The first MIS transistor includes a first gate insulating film, and a first gate electrode including a first metal film and a first silicon film. The second MIS transistor includes a second gate insulating film, and a second gate electrode including the first metal film, a second metal film, and a second silicon film.

Abstract: A semiconductor device includes a first MIS transistor formed on a first active region, and a second MIS transistor formed on a second active region. The first MIS transistor includes a first gate insulating film, and a first gate electrode including a first metal film and a first silicon film. The second MIS transistor includes a second gate insulating film, and a second gate electrode including the first metal film, a second metal film, and a second silicon film.

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract: A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.

Abstract: In a semiconductor device according to the present invention, the power source voltage Vdd1 of a core transistor Tr1, the power source voltage Vdd2 of an I/O transistor Tr2, and the power source voltage Vdd3 of an I/O transistor Tr3 satisfy Vdd1<Vdd2<Vdd3. In a method for fabricating the semiconductor device, each of the respective gate insulating films of the I/O transistors Tr2 and Tr3 is formed in the same step to have the same thickness. Each of the respective SD extension regions of the core transistor Tr1 and the I/O transistor Tr2 is formed at the same dose.

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract: In a MIEET, an impurity which changes a lattice constant is introduced into part of a gate electrode located on an isolation region. A stress which is generated in part of the gate electrode as a starting point and improves the mobility of carries is applied to a channel region with the part of the gate electrode.

Abstract: A first semiconductor region has a smaller width along a gate length direction than a second semiconductor region. In this case, the first semiconductor region has a larger width along a gate width direction than the second semiconductor region.

Abstract: In a semiconductor device according to the present invention, the power source voltage Vdd1 of a core transistor Tr1, the power source voltage Vdd2 of an I/O transistor Tr2, and the power source voltage Vdd3 of an I/O transistor Tr3 satisfy Vdd1<Vdd2<Vdd3. In a method for fabricating the semiconductor device, each of the respective gate insulating films of the I/O transistors Tr2 and Tr3 is formed in the same step to have the same thickness. Each of the respective SD extension regions of the core transistor Tr1 and the I/O transistor Tr2 is formed at the same dose.

Abstract: As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.

Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Abstract: A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

Abstract: A semiconductor device includes a semiconductor substrate; a diffusion region which is formed in the semiconductor substrate and serves as a region for the formation of a MIS transistor; an element isolation region surrounding the diffusion region; at least one gate conductor film which is formed across the diffusion region and the element isolation region, includes a gate electrode part located on the diffusion region and a gate interconnect part located on the element isolation region, and has a constant dimension in the gate length direction; and an interlayer insulating film covering the gate electrode. The semiconductor device further includes a gate contact which passes through the interlayer insulating film, is connected to the gate interconnect part, and has the dimension in the gate length direction larger than the gate interconnect part.

Abstract: A first relational expression representing a relationship among gate bias Vd, carrier mobility ?, electric effective channel length Leff and transconductance Gm, and a second relational expression representing a relationship among maximum-transconductance ratio Gmmax L=Lref/Gmmax L=Ltar between a target transistor and a reference transistor and electric effective channel lengths Leff and Lref of the respective transistors are used. Maximum transconductance Gmmax obtained when gate bias Vd is changed is determined and electric effective channel length Leff is estimated by substituting the value of maximum transconductance Gmmax in the second relational expression. The correlation between 1/Gmmax and Lgsem is strong enough to allow maximum transconductance Gmmax to be used in monitoring a process variation of a physical gate length.

Abstract: With this method for manufacturing a semiconductor device, a gate insulating film is formed on a semiconductor substrate, and a polysilicon thin film is formed on the gate insulating film. A plasma nitriding process is then performed, thereby introducing nitrogen into the polysilicon thin film. A polysilicon film is next formed on the polysilicon thin film and the plasma nitriding process is performed, thereby forming a nitrogen-containing region having a depth of 10 nm or less in an upper portion of the polysilicon film. The polysilicon film is patterned to form a gate electrode. SD extensions are then formed in the semiconductor substrate, a sidewall is formed on a side surface of the gate electrode, and source and drain regions are then formed in the semiconductor substrate.

Abstract: As first thermal treatment for activating an impurity injected into a gate electrode, thermal treatment at a low temperature for a long time in which boron diffusion into each crystal grain in polysilicon hardly occurs and boron diffusion in each crystal boundary occurs is performed. Next, as second thermal treatment, thermal treatment at a high temperature for a short time, such as spike annealing and flash annealing, in which impurity diffusion into each crystal grain in a polysilicon layer occurs is performed.

Abstract: A single evaluation portion is formed by disposing a plurality of MIS transistors used for evaluation having substantially the same structure as that of an actually used MIS transistor. In the evaluation portion, the respective source regions, drain regions, and gate electrodes of the MIS transistors used for evaluation are electrically connected in common to a source pad, a drain pad, and a gate pad, respectively. If the effective gate width of the single evaluation portion exceeds a given value, variations in characteristics evaluated by the evaluation portion approach variations in the characteristics of the entire semiconductor device. The accuracy of evaluating the characteristics of the semiconductor device can thus be improved by using the evaluation portion.

Abstract: A memory cell transistor and a planar capacitor are provided in a memory region, and both transistors of a CMOS device are provided in a logic circuit region. A capacitance dielectric 15 and a plate electrode 16b of the planar capacitor are provided over a trench shared with a shallow trench isolation 12a, and the upper part of the trench is filled with the capacitance dielectric 15 and the plate electrode 16b. An n-type diffusion layer 19 that is a storage node is formed, with an end region thereof extending along one side of the upper part of the trench, to a region of the substrate overlapping with the shallow trench isolation 12a. The area of a part of the substrate functioning as a capacitor can be increased without increasing the substrate area.

Abstract: A manufacturing method for a semiconductor device, whereby poly-silicon serving as an etching stopper is formed above a redundant fuse at the same time as a cell plate is. A silicon nitride film, an oxide film, and another oxide film on the redundant fuse are consecutively etched using the poly-silicon as the etching stopper. Then the poly-silicon is etched.