Abstract: A vital data acquisition system includes a hardware processor that: sets an identified region, based on imaged information; acquires vital data based on a detection result from a sensor; and determines whether the identified region is correctly set based on the vital data.

Abstract: There is an image data processing circuit including a memory storing input image data, the input image data being limited to a specific number of colors or to a specific image range, and a correction processing part replacing, when a predetermined tone change is present between a pixel in image data previous by one frame whose data is stored by the memory and a pixel in image data in a current frame whose data is input, a relevant pixel in the current frame with a color of a specific tone. The memory is built in an integrated circuit included in the correction processing part.

Abstract: Disclosed herein is a data reception circuit including a clock generation block configured to divide a first clock based on clock information, the first clock being the clock of a transmission stream targeted to transmit video data between apparatuses, the clock information indicating a cyclical relationship between the first clock and a second clock serving as the clock of predetermined data, the clock generation block further outputting the divided clock as the second clock.

Abstract: There is an image data processing circuit including a memory storing input image data, the input image data being limited to a specific number of colors or to a specific image range, and a correction processing part replacing, when a predetermined tone change is present between a pixel in image data previous by one frame whose data is stored by the memory and a pixel in image data in a current frame whose data is input, a relevant pixel in the current frame with a color of a specific tone. The memory is built in an integrated circuit included in the correction processing part.

Abstract: Disclosed herein is a data reception circuit including a clock generation block configured to divide a first clock based on clock information, the first clock being the clock of a transmission stream targeted to transmit video data between apparatuses, the clock information indicating a cyclical relationship between the first clock and a second clock serving as the clock of predetermined data, the clock generation block further outputting the divided clock as the second clock.