Patents by Inventor Atsuhiro Nishida

Atsuhiro Nishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7683268
    Abstract: A semiconductor element and a passive element are embedded in an insulating resin film by thermocompression bonding. After formation of a interconnection, a layered film which contains a film insulating between elements and is provided with a recess or penetrated portion is pressure-bonded followed by formation of a member with a high resistance or a high dielectric constant by embedding a material of a member constituting an element such as a resistor and a capacitor in the recess. Furthermore, after formation of the upper layer insulating resin film, a photoimageable solder resist layer containing the cardo type polymer is formed, and interconnection formation and solder electrode formation are performed.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: March 23, 2010
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Takeshi Nakamura, Atsuhiro Nishida
  • Patent number: 7495344
    Abstract: A semiconductor apparatus includes a substrate and elements or semiconductor chips provided on the substrate. The elements are sealed by being brought into contact with a sealing compound. The surface of contact on the elements or the sealing compound is plasma treated. The semiconductor chip is adhesively attached to another semiconductor chip via an adhesive compound. The surface of the semiconductor chip in contact with the adhesive compound is plasma treated.
    Type: Grant
    Filed: March 16, 2005
    Date of Patent: February 24, 2009
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Ryosuke Usui, Atsuhiro Nishida, Hideki Mizuhara, Takeshi Nakamura
  • Publication number: 20050269128
    Abstract: A semiconductor element and a passive element are embedded in an insulating resin film by thermocompression bonding. After formation of a interconnection, a layered film which contains a film insulating between elements and is provided with a recess or penetrated portion is pressure-bonded followed by formation of a member with a high resistance or a high dielectric constant by embedding a material of a member constituting an element such as a resistor and a capacitor in the recess. Furthermore, after formation of the upper layer insulating resin film, a photoimageable solder resist layer containing the cardo type polymer is formed, and interconnection formation and solder electrode formation are performed.
    Type: Application
    Filed: June 7, 2005
    Publication date: December 8, 2005
    Inventors: Ryosuke Usui, Takeshi Nakamura, Atsuhiro Nishida
  • Publication number: 20050205996
    Abstract: A semiconductor apparatus includes a substrate and elements or semiconductor chips provided on the substrate. The elements are sealed by being brought into contact with a sealing compound. The surface of contact on the elements or the sealing compound is plasma treated. The semiconductor chip is adhesively attached to another semiconductor chip via an adhesive compound. The surface of the semiconductor chip in contact with the adhesive compound is plasma treated.
    Type: Application
    Filed: March 16, 2005
    Publication date: September 22, 2005
    Inventors: Ryosuke Usui, Atsuhiro Nishida, Hideki Mizuhara, Takeshi Nakamura
  • Patent number: 6803636
    Abstract: A semiconductor device capable of easily setting the sheet resistance of a resistive element or the like to an arbitrary value is obtained. This semiconductor device comprises a first silicide film formed on a first silicon region and a second silicide film, formed on a second silicon region, consisting of the same silicide material as the first silicide film and differing from the first silicide film in film quality to have a sheet resistance value different from that of the first silicide film. When an impurity is introduced into the second silicide film itself so that the second silicide film differs from the first silicide film in film quality in this case, for example, a second silicide film having an arbitrary high sheet resistance value can be obtained by controlling the type of and an introduction condition for the impurity.
    Type: Grant
    Filed: September 16, 2002
    Date of Patent: October 12, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yoshikazu Ibara, Atsuhiro Nishida
  • Patent number: 6794283
    Abstract: A semiconductor device superior in reliability and suitable for microminiaturization is provided. An organic SOG film is formed on a silicon oxide film. Boron ions are implanted into the organic SOG film. By introducing boron ions into the organic SOG film, the organic components in the film are decomposed. Also, the moisture and hydroxyl group included in the film are reduced. After a metal interconnection is embedded in a modified SOG film by the Damascene method, a modified SOG film is formed thereon. Then, contact holes are formed. After a contact hole interconnection is embedded in the contact holes, a modified SOG film and an upper metal interconnection are formed by the Damascene method.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: September 21, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroyuki Watanabe, Hideki Mizuhara, Shinichi Tanimoto, Atsuhiro Nishida, Yoshikazu Yamaoka, Yasunori Inoue
  • Publication number: 20030052372
    Abstract: A semiconductor device capable of easily setting the sheet resistance of a resistive element or the like to an arbitrary value is obtained. This semiconductor device comprises a first silicide film formed on a first silicon region and a second silicide film, formed on a second silicon region, consisting of the same silicide material as the first silicide film and differing from the first silicide film in film quality to have a sheet resistance value different from that of the first silicide film. When an impurity is introduced into the second silicide film itself so that the second silicide film differs from the first silicide film in film quality in this case, for example, a second silicide film having an arbitrary high sheet resistance value can be obtained by controlling the type of and an introduction condition for the impurity.
    Type: Application
    Filed: September 16, 2002
    Publication date: March 20, 2003
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yoshikazu Ibara, Atsuhiro Nishida
  • Patent number: 6342440
    Abstract: A method of manufacturing a semiconductor device capable of suppressing increase of a leakage current resulting from a high-temperature heat treatment is obtained. In this manufacturing method, an impurity region is formed by selectively ion-implanting an impurity into the main surface of a semiconductor substrate. The impurity region is activated by performing a high-temperature heat treatment. The semiconductor device is recovered from crystal defects resulting from the high-temperature heat treatment by performing a low-temperature heat treatment after performing the high-temperature heat treatment. According to this manufacturing method, the semiconductor device is recovered from the crystal defects resulting from the ion implantation by the high-temperature heat treatment, and recovered from the crystal defects resulting from the high-temperature heat treatment by the low-temperature heat treatment.
    Type: Grant
    Filed: March 3, 2000
    Date of Patent: January 29, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazuhiro Sasada, Yasunori Inoue, Shinichi Tanimoto, Atsuhiro Nishida, Yoshikazu Ibara
  • Publication number: 20010055873
    Abstract: A semiconductor device superior in reliability and suitable for microminiaturization is provided. An organic SOG film is formed on a silicon oxide film. Boron ions are implanted into the organic SOG film. By introducing boron ions into the organic SOG film, the organic components in the film are decomposed. Also, the moisture and hydroxyl group included in the film are reduced. After a metal interconnection is embedded in a modified SOG film by the Damascene method, a modified SOG film is formed thereon. Then, contact holes are formed. After a contact hole interconnection is embedded in the contact holes, a modified SOG film and an upper metal interconnection are formed by the Damascene method.
    Type: Application
    Filed: May 27, 1999
    Publication date: December 27, 2001
    Inventors: HIROYUKI WATANABE, HIDEKI MIZUHARA, SHINICHI TANIMOTO, ATSUHIRO NISHIDA, YOSHIKAZU YAMAOKA, YASUNORI INOUE
  • Patent number: 5936300
    Abstract: A pair of source/drain regions are formed on a semiconductor substrate at a predetermined interval. A gate insulator film is formed on the semiconductor substrate between the source/drain regions of the pair. A gate electrode is formed on the gate insulator film. A film for covering the gate electrode and the source/drain regions has a low permeability against water and a hydroxide group, and has a thickness greater than 3 nm and less than 5 nm.
    Type: Grant
    Filed: March 24, 1997
    Date of Patent: August 10, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kazuhiro Sasada, Mamoru Arimoto, Hideharu Nagasawa, Atsuhiro Nishida, Hiroyuki Aoe, Yosifumi Matusita