Patents by Inventor Atsuhiro Sato
Atsuhiro Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7012295Abstract: The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.Type: GrantFiled: June 29, 2004Date of Patent: March 14, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Makoto Sakuma, Fumitaka Arai
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Publication number: 20060033151Abstract: A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.Type: ApplicationFiled: October 27, 2005Publication date: February 16, 2006Inventors: Riichiro Shirota, Kikuko Sugimae, Masayuki Ichige, Atsuhiro Sato, Hiroaki Hazama
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Patent number: 6977409Abstract: A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.Type: GrantFiled: October 16, 2003Date of Patent: December 20, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Riichiro Shirota, Kikuko Sugimae, Masayuki Ichige, Atsuhiro Sato, Hiroaki Hazama
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Publication number: 20050199938Abstract: A nonvolatile semiconductor memory includes a plurality of memory cell transistors configured with a first floating gate, a first control gate, and a first inter-gate insulating film each arranged between the first floating gate and the first control gate, respectively, and which are aligned along a bit line direction; device isolating regions disposed at a constant pitch along a word line direction making a striped pattern along the bit line direction; and select gate transistors disposed at each end of the alignment of the memory cell transistors, each configured with a second floating gate, a second control gate, a second inter-gate insulator film disposed between the second floating gate and the second control gate, and a sidewall gate electrically connected to the second floating gate and the second control gate.Type: ApplicationFiled: October 25, 2004Publication date: September 15, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Makoto Sakuma, Atsuhiro Sato
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Patent number: 6927139Abstract: A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.Type: GrantFiled: November 21, 2003Date of Patent: August 9, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Atsuhiro Sato, Hiroki Yamashita, Ichiro Mizushima, Yoshio Ozawa
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Patent number: 6921960Abstract: A semiconductor device includes a structure in which a first electrode layer, an inter-electrode insulating film and a second electrode layer are laminated in a main circuit in this order, and includes a capacitor element having a lower electrode formed of the same layer as the first electrode layer, a charge storage layer formed of the same layer as the inter-electrode insulating film, and an upper electrode formed of the second electrode layer. The semiconductor device further includes an opening portion formed in the charge storage layer, the opening portion having a bottom to which the lower electrode is exposed, and a first region electrically connected to the lower electrode via the opening portion and electrically isolated from the upper electrode, the first region being formed of the same layer as the second electrode layer.Type: GrantFiled: October 31, 2001Date of Patent: July 26, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ichige, Riichiro Shirota, Kikuko Sugimae, Atsuhiro Sato, Yuji Takeuchi
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Publication number: 20050104120Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.Type: ApplicationFiled: December 27, 2004Publication date: May 19, 2005Inventors: Masayuki Ichige, Yuji Takeuchi, Michiharu Matsui, Atsuhiro Sato, Kikuko Sugimae, Riichiro Shirota
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Publication number: 20050105336Abstract: A semiconductor memory includes a memory cell array having a memory cell units, configured from memory cell transistors connected in a column, which have a first and a second control gate disposed on both sides of a floating gate horizontally arranged with a first end connected to a bit line via a first select-gate transistor, and a second end connected to a source line via a second select-gate transistor. The first and the second control gate of memory cell transistors arranged in the same row are connected in common to a first and a second control gate line in a row, respectively. It also includes a boosting circuit, which generates a write-in voltage, multilevel intermediate voltages, and a bit line voltage from a power source, and a row decoder supplied with the write-in voltage and the multilevel intermediate voltages to select the first and the second control gate.Type: ApplicationFiled: September 21, 2004Publication date: May 19, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro Sato, Yasuhiko Matsunaga, Fumitaka Arai
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Publication number: 20050094431Abstract: A nonvolatile semiconductor memory includes: a memory sub array including a memory cell unit configured with a memory cell transistor and a select transistor connected in series; a control gate line driver including a control gate line driver transistor connected to a control gate line of the memory cell transistor; and a select transistor gate line driver including a select gate line driver transistor connected to a select gate line of the select transistor. A thickness of a gate insulator of the control gate line driver transistor is thicker than that of the select gate line driver transistor.Type: ApplicationFiled: September 24, 2004Publication date: May 5, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro Sato, Riichiro Shirota, Kikuko Sugimae, Koji Sakui
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Publication number: 20050067652Abstract: A nonvolatile semiconductor memory includes a plurality of memory cell transistors, having floating gates, control gates, and inter-gate insulating films each arranged between corresponding floating gate and corresponding control gate, respectively, and deployed along a column direction; and device isolation regions deployed at a constant pitch along a row direction making a striped pattern along the column direction. The control gates are continuously deployed along the row direction, and the inter-gate insulating films are in series along the column direction and separated from each other at a constant pitch along the row direction.Type: ApplicationFiled: June 17, 2004Publication date: March 31, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Makoto Sakuma, Atsuhiro Sato
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Publication number: 20050045966Abstract: A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.Type: ApplicationFiled: June 17, 2004Publication date: March 3, 2005Applicant: Kabushiki Kaisha ToshibaInventors: Hiroki Yamashita, Yoshio Ozawa, Atsuhiro Sato
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Publication number: 20050029573Abstract: The memory cell transistor has a first cell site gate insulator, a first lower conductive layer on the first cell site gate insulator, a first inter-electrode dielectric on the first lower conductive layer, and a first upper conductive layer on the first inter-electrode dielectric. A select transistor has a second cell site gate insulator having a same thickness as the first cell site gate insulator, a second lower conductive layer on the second cell site gate insulator, a second inter-electrode dielectric on the second lower conductive layer, and a second upper conductive layer on the second inter-electrode dielectric. The peripheral transistor has a first peripheral site gate insulator having a thickness thinner than the first cell site gate insulator.Type: ApplicationFiled: June 29, 2004Publication date: February 10, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro Sato, Makoto Sakuma, Fumitaka Arai
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Patent number: 6853029Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.Type: GrantFiled: May 28, 2002Date of Patent: February 8, 2005Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Ichige, Yuji Takeuchi, Michiharu Matsui, Atsuhiro Sato, Kikuko Sugimae, Riichiro Shirota
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Publication number: 20050003619Abstract: A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.Type: ApplicationFiled: November 21, 2003Publication date: January 6, 2005Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Masayuki Tanaka, Atsuhiro Sato, Hiroki Yamashita, Ichiro Mizushima, Yoshio Ozawa
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Patent number: 6798038Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: GrantFiled: May 9, 2002Date of Patent: September 28, 2004Assignee: Kabushiki Kaisha ToshibaInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Publication number: 20040173870Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: ApplicationFiled: March 15, 2004Publication date: September 9, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Publication number: 20040081002Abstract: A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.Type: ApplicationFiled: October 16, 2003Publication date: April 29, 2004Inventors: Riichiro Shirota, Kikuko Sugimae, Masayuki Ichige, Atsuhiro Sato, Hiroaki Hazama
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Patent number: 6667507Abstract: A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.Type: GrantFiled: July 6, 2001Date of Patent: December 23, 2003Assignee: Kabushiki Kaisha ToshibaInventors: Riichiro Shirota, Kikuko Sugimae, Masayuki Ichige, Atsuhiro Sato, Hiroaki Hazama
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Publication number: 20030052384Abstract: Forming of a first silicon oxide film is started on an internal surface of a trench formed on a surface or upwardly of a semiconductor substrate according to an HDP technique. Then, deposition of the first silicon oxide film stops before an opening of the trench closes. Further, the first silicon oxide film deposited in the vicinity of an opening is etched, and a second silicon oxide film is formed on the first silicon oxide film deposited on the bottom of the trench according to the HDP technique. In this manner, the first and second silicon oxide films can be laminated on the bottom of the trench.Type: ApplicationFiled: May 9, 2002Publication date: March 20, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Atsuhiro Sato, Masayuki Ichige, Seiichi Mori, Yuji Takeuchi, Hiroaki Hazama, Yukio Nishiyama, Hirotaka Ogihara, Naruhiko Kaji
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Publication number: 20020175364Abstract: A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.Type: ApplicationFiled: May 28, 2002Publication date: November 28, 2002Inventors: Masayuki Ichige, Yuji Takeuchi, Michiharu Matsui, Atsuhiro Sato, Kikuko Sugimae, Riichiro Shirota