Abstract: To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.

Abstract: A multicore processor system includes plural CPUs; branch prediction memories respectively disposed for the CPUs; and a shared branch prediction memory that stores branch prediction information records respectively corresponding to threads executed by the CPUs. A first CPU among the CPUs is configured to set the branch prediction information record corresponding to a first thread among the threads executed by the first CPU, from the shared branch prediction memory to the branch prediction memory corresponding to the first CPU.

Abstract: According to one aspect of embodiments, a multiprocessor system includes a cache memory corresponding to each of the processors, a hierarchy setting register in which the hierarchical level of each cache memory is set, an access control unit that controls access between each cache memory. The hierarchical level of the cache memory for each processor is stored in a rewritable hierarchy setting register. Each processor handles a cache memory corresponding to another processor as the cache memory having a deeper hierarchy than the cache memory corresponding to the each processor. As the result, each processor can access all the cache memories, and therefore the efficiency of cache memory utilization can be improved and the hierarchical level can be set so that the latency becomes optimal for each application.

Abstract: A dependent element group which is invertibly contractible is found by using program analysis information including a plurality of dependent elements representing dependent relationships of statement and control, the statement and the control being included in a program. Next, a program dependence graph in which dependent elements are made to be contracted is generated by contracting the found dependent element group. The number of vertices and the number of edges of the program dependence graph are reduced by the contraction of the dependent elements, so that a program dependence graph with a rough granularity can be generated. As a result, a calculation amount (calculation time) necessary for optimization processing such as parallel processing of the program can be reduced. That is, by generating the contracted program dependence graph having invertibility, it is possible to realize the analysis and optimization of large-scale software in a realistic time.

Abstract: To provide a program performance analysis apparatus that can present to a user whether tuning made to a program operating on a predetermined hardware is either good or bad, a performance information acquisition unit for obtaining the performance information of a program, a difference information generation unit for generating difference information by making a comparison between the performance information of a first program and that of a second program obtained by making a change to the first program, and a change evaluation unit for evaluating whether the change is either good or bad are comprised.

Abstract: When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.

Abstract: A dependent element group which is invertibly contractible is found by using program analysis information including a plurality of dependent elements representing dependent relationships of statement and control, the statement and the control being included in a program. Next, a program dependence graph in which dependent elements are made to be contracted is generated by contracting the found dependent element group. The number of vertices and the number of edges of the program dependence graph are reduced by the contraction of the dependent elements, so that a program dependence graph with a rough granularity can be generated. As a result, a calculation amount (calculation time) necessary for optimization processing such as parallel processing of the program can be reduced. That is, by generating the contracted program dependence graph having invertibility, it is possible to realize the analysis and optimization of large-scale software in a realistic time.

Abstract: According to one aspect of embodiments, a multiprocessor system includes a cache memory corresponding to each of the processors, a hierarchy setting register in which the hierarchical level of each cache memory is set, an access control unit that controls access between each cache memory. The hierarchical level of the cache memory for each processor is stored in a rewritable hierarchy setting register. Each processor handles a cache memory corresponding to another processor as the cache memory having a deeper hierarchy than the cache memory corresponding to the each processor. As the result, each processor can access all the cache memories, and therefore the efficiency of cache memory utilization can be improved and the hierarchical level can be set so that the latency becomes optimal for each application.

Abstract: A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.

Abstract: A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.

Abstract: In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.

Abstract: An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.

Abstract: The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target addre

Abstract: When an input address AD is previously stored in a register 211, if a matching signal EQ1 is active, then an address queue control circuit 19A latches an offset of the input address AD into a register 241, or else, latches the input address AD into a register 212 through a selector 262. When the input address AD is previously stored in the register 241, the address queue control circuit 19A latches the input address AD into the register 212 through the selector 262. After reading the contents of the register 211, the address queue control circuit 19A shifts the offset OFS of the register 241 to the offset field of the register 211 through a selector 261, and resets a valid flag EF of the register 241.

Abstract: In a computer system having a plurality of processing elements (PE#0 to PE#n) and adopting a distributed-shared-memory-type multiprocessor scheme, a master PE (for example, PE#0) executing a multi PE loader transfers an MPMD program for PE#k to a predetermined area of memory space of PE#0 to which a unique memory (LM) of PE#k is temporally allocated. The LMs of PE#1 to PE#n can be allocated to different areas of the memory space of PE#0 respectively, or can be allocated the same area thereof.

Abstract: The present invention relates to a processor that performs a load operation prior to a store operation while avoiding ambiguous memory reference, and achieves high-speed operations. The present invention also relates to a method of controlling such a processor. This processor includes a history control unit that stores a storage destination of a result obtained by executing a second instruction that is executed prior to a first instruction placed before the second instruction. When it is determined that the address of first data to be processed by the first instruction is included in the address region of second data to be processed by the second instruction, the history control unit overwrites the result obtained by the execution of the first instruction on the second data corresponding to the address.

Abstract: In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.

Abstract: The present invention provides a processor system having a main processor that efficiently executes coprocessor instructions, regardless of the type of each coprocessor to which the main processor is connected. When a coprocessor instruction to instruct execution by a coprocessor is supplied, the main processor determines whether or not the supplied coprocessor instruction has a possibility of having control dependency on a preceding coprocessor instruction being executed by a corresponding one of the coprocessor, in accordance with an instruction field corresponding to the supplied coprocessor instruction. If the supplied coprocessor instruction has the possibility of having the control dependency, the main processor issues the supplied coprocessor to the corresponding one of the processors only after the execution of the preceding coprocessor instruction is completed.

Abstract: A central processing unit (GT) comprises a private key in secrecy, and an encryption engine. Before the GT executes software, a license added to the software is entered into the GT. The license includes information obtained by encrypting a code encryption key used when the software is encrypted with a public key pairing with the private key. When the license is entered, the encryption engine obtains the code encryption key by decrypting the license with the private key, and decrypts the software with the code encryption key.

Abstract: When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.