Patents by Inventor Atsuhito Murai

Atsuhito Murai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11751451
    Abstract: According to one embodiment, a display device includes a pixel area including pixels each including at least one thin film transistor includes a semiconductor layer and a gate electrode, a first terminal area including a first wiring line disposed thereon connected to the at least one thin film transistor, a first protective film provided on the semiconductor layer, the gate electrode and the first wiring line, a first insulating film provided on the first protective film, a second protective film provided on the first insulating film, a second insulating film provided on the second protective film, a first opening formed in the first terminal area, and partially exposing the first wiring line, and a second opening formed to correspond to the first opening.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: September 5, 2023
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Eiichi Sato, Masanori Miura
  • Patent number: 11678539
    Abstract: A display unit includes a substrate including a pixel region including a plurality of pixels and a peripheral region. The display unit includes a plurality of first electrodes, wherein each of the plurality of first electrodes is in a corresponding pixel of the plurality of pixels. The display unit includes a second electrode opposed to the first electrode, wherein the second electrode is common for all of the plurality of pixels. The display unit includes an organic layer between the second electrode and the plurality of first electrodes, wherein the organic layer includes a light-emitting layer. The display unit includes a wiring layer between the substrate and the plurality of first electrodes. The display unit includes an auxiliary electrically-conductive layer including an organic electrically-conductive material, wherein the auxiliary electrically-conductive layer is electrically coupled to the second electrode. The auxiliary electrically-conductive layer is in a recess in the wiring layer.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: June 13, 2023
    Assignee: JOLED INC.
    Inventors: Yasuhiro Terai, Yasuharu Shinokawa, Jiro Yamada, Atsuhito Murai, Masahiko Kondo, Noriteru Maeda
  • Publication number: 20220085139
    Abstract: A display unit includes a substrate including a pixel region including a plurality of pixels and a peripheral region. The display unit includes a plurality of first electrodes, wherein each of the plurality of first electrodes is in a corresponding pixel of the plurality of pixels. The display unit includes a second electrode opposed to the first electrode, wherein the second electrode is common for all of the plurality of pixels. The display unit includes an organic layer between the second electrode and the plurality of first electrodes, wherein the organic layer includes a light-emitting layer. The display unit includes a wiring layer between the substrate and the plurality of first electrodes. The display unit includes an auxiliary electrically-conductive layer including an organic electrically-conductive material, wherein the auxiliary electrically-conductive layer is electrically coupled to the second electrode. The auxiliary electrically-conductive layer is in a recess in the wiring layer.
    Type: Application
    Filed: November 24, 2021
    Publication date: March 17, 2022
    Inventors: Yasuhiro TERAI, Yasuharu SHINOKAWA, Jiro YAMADA, Atsuhito MURAI, Masahiko KONDO, Noriteru MAEDA
  • Publication number: 20220005918
    Abstract: According to one embodiment, a display device includes a pixel area including pixels each including at least one thin film transistor includes a semiconductor layer and a gate electrode, a first terminal area including a first wiring line disposed thereon connected to the at least one thin film transistor, a first protective film provided on the semiconductor layer, the gate electrode and the first wiring line, a first insulating film provided on the first protective film, a second protective film provided on the first insulating film, a second insulating film provided on the second protective film, a first opening formed in the first terminal area, and partially exposing the first wiring line, and a second opening formed to correspond to the first opening.
    Type: Application
    Filed: September 21, 2021
    Publication date: January 6, 2022
    Inventors: Atsuhito MURAI, Eiichi SATO, Masanori MIURA
  • Patent number: 11217650
    Abstract: A display unit includes a substrate, a first electrode, a second electrode, an organic layer, and an auxiliary electrically-conductive layer. The substrate includes a pixel region including a plurality of pixels and a peripheral region outside the pixel region. The first electrode is provided for each of the plurality of pixels in the pixel region on the substrate. The second electrode is opposed to the first electrode, and is provided common for the plurality of pixels. The organic layer is provided between the second electrode and the first electrode, and includes a light-emitting layer. The auxiliary electrically-conductive layer includes an organic electrically-conductive material, and the auxiliary electrically-conductive layer is disposed in the pixel region on the substrate and is electrically coupled to the second electrode.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: January 4, 2022
    Assignee: JOLED INC.
    Inventors: Yasuhiro Terai, Yasuharu Shinokawa, Jiro Yamada, Atsuhito Murai, Masahiko Kondo, Noriteru Maeda
  • Patent number: 11217641
    Abstract: A display unit includes multiple pixels, a first electrode, a partition wall, a light emission layer, and a second electrode. The multiple pixels each have a light emission region and a non-light emission region along a first direction. The first electrode is provided in the light emission region in each of the multiple pixels. The partition wall is provided between each two of the pixels that are adjacent to each other in a second direction. The second direction intersects the first direction. The light emission layer covers the first electrode and is provided in the light emission region and the non-light emission region in a continuous manner. The second electrode faces the first electrode across the light emission layer.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: January 4, 2022
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Jiro Yamada, Yasuhiro Terai, Masahiko Kondo, Noriteru Maeda
  • Patent number: 11152447
    Abstract: According to one embodiment, a display device includes a pixel area including pixels each including at least one thin film transistor includes a semiconductor layer and a gate electrode, a first terminal area including a first wiring line disposed thereon connected to the at least one thin film transistor, a first protective film provided on the semiconductor layer, the gate electrode and the first wiring line, a first insulating film provided on the first protective film, a second protective film provided on the first insulating film, a second insulating film provided on the second protective film, a first opening formed in the first terminal area, and partially exposing the first wiring line, and a second opening formed to correspond to the first opening.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: October 19, 2021
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Eiichi Sato, Masanori Miura
  • Patent number: 11063109
    Abstract: A display unit includes a first substrate, a transistor, first and second wiring layers, and an insulating film. The first substrate is provided with a display region and a peripheral region. The transistor is provided in the display region, and includes a semiconductor layer, a gate electrode facing the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and a source-drain electrode electrically coupled to the semiconductor layer. The first wiring layer is provided in the peripheral region, electrically coupled to the transistor, and disposed closer to the first substrate than the same layer as the gate electrode and the source-drain electrode. The second wiring layer is provided on the first substrate and has an electric potential different from the first wiring layer. The insulating film is provided between the second wiring layer and the first wiring layer.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: July 13, 2021
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Yasuhiro Terai, Takashi Maruyama, Yoshihiro Oshima, Motohiro Toyota, Ryosuke Ebihara, Yasunobu Hiromasu
  • Patent number: 11018160
    Abstract: A thin-film transistor substrate includes a pixel circuit, an interlayer insulating film, electrodes, and a hard mask metal. The pixel circuit includes a thin film transistor. The interlayer insulating film has contact holes and covers the pixel circuit. The electrodes are exposed above a surface of the interlayer insulating film, and electrically coupled to the pixel circuit via the contact holes. The hard mask metal has openings at portions facing the contact holes and is provided on the surface of the interlayer insulating film.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: May 25, 2021
    Assignee: JOLED INC.
    Inventors: Ryosuke Ebihara, Yasuhiro Terai, Atsuhito Murai
  • Patent number: 10839745
    Abstract: A display unit includes a display panel, a photochromic layer, and an ultraviolet absorption layer. The photochromic layer is configured to be colored by ultraviolet light and be decolored or color-faded by visible light. The display panel includes an image display surface with a plurality of pixels. The pixels are provided below the image display surface and each include an organic light-emitting layer.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: November 17, 2020
    Assignee: JOLED INC.
    Inventors: Masahiko Kondo, Jiro Yamada, Atsuhito Murai, Yasuhiro Terai, Noriteru Maeda
  • Patent number: 10811445
    Abstract: A semiconductor device includes a substrate. The semiconductor device further includes a first transistor. The first transistor includes a first semiconductor layer over the substrate, the first semiconductor layer including poly-silicon. The first transistor further includes a first gate electrode over the first semiconductor layer, the first gate electrode facing the first semiconductor layer. The semiconductor device further includes a second transistor. The second transistor includes a second semiconductor layer over the substrate, the second semiconductor layer including an oxide semiconductor. The second transistor further includes a second gate electrode over the second semiconductor layer, the second gate electrode facing the second semiconductor layer.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 20, 2020
    Assignee: JOLED INC.
    Inventor: Atsuhito Murai
  • Publication number: 20200227511
    Abstract: A display unit includes a first substrate, a transistor, first and second wiring layers, and an insulating film. The first substrate is provided with a display region and a peripheral region. The transistor is provided in the display region, and includes a semiconductor layer, a gate electrode facing the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and a source-drain electrode electrically coupled to the semiconductor layer. The first wiring layer is provided in the peripheral region, electrically coupled to the transistor, and disposed closer to the first substrate than the same layer as the gate electrode and the source-drain electrode. The second wiring layer is provided on the first substrate and has an electric potential different from the first wiring layer. The insulating film is provided between the second wiring layer and the first wiring layer.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: Atsuhito MURAI, Yasuhiro TERAI, Takashi MARUYAMA, Yoshihiro OSHIMA, Motohiro TOYOTA, Ryosuke EBIHARA, Yasunobu HIROMASU
  • Patent number: 10680197
    Abstract: A display device includes a display region, an organic insulating layer, a display element, and a moisture-ingress barrier. The organic insulating layer has a groove outside the display region. The organic insulating layer extends over the display region and a region outside the groove. The display element is disposed in the display region and includes, in order, a first electrode, an organic layer, and a second electrode. The organic layer includes one or more moisture-reacting layers. The moisture-ingress barrier is disposed in the groove of the organic insulating layer, includes a material identical to the material of the one or more moisture-reacting layers, and has a thickness greater than the thickness of the one or more moisture-reacting layers.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: June 9, 2020
    Assignee: JOLED INC.
    Inventors: Masanori Miura, Atsuhito Murai
  • Patent number: 10644093
    Abstract: A display unit includes a first substrate, a transistor, first and second wiring layers, and an insulating film. The first substrate is provided with a display region and a peripheral region. The transistor is provided in the display region, and includes a semiconductor layer, a gate electrode facing the semiconductor layer, a gate insulating film between the gate electrode and the semiconductor layer, and a source-drain electrode electrically coupled to the semiconductor layer. The first wiring layer is provided in the peripheral region, electrically coupled to the transistor, and disposed closer to the first substrate than the same layer as the gate electrode and the source-drain electrode. The second wiring layer is provided on the first substrate and has an electric potential different from the first wiring layer. The insulating film is provided between the second wiring layer and the first wiring layer.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: May 5, 2020
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Yasuhiro Terai, Takashi Maruyama, Yoshihiro Oshima, Motohiro Toyota, Ryosuke Ebihara, Yasunobu Hiromasu
  • Patent number: 10580799
    Abstract: According to one embodiment, a thin film transistor includes an oxide semiconductor layer provided above an insulating substrate and including a channel region between a source region and a drain region, a first insulating film provided in a region on the oxide semiconductor layer, which corresponds to the channel region, a gate electrode provided on the first insulating film, a first protective film provided on the oxide semiconductor layer, the first insulating film and the gate electrode, as an insulating film containing a metal, a second protective film provided on the first protective film and a third protective film provided on the second protective film, as an insulating film containing a metal.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: March 3, 2020
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Eiichi Sato, Masanori Miura
  • Patent number: 10546538
    Abstract: A display apparatus includes a display panel and a driving circuit. The display panel includes signal lines extending in a column direction, scanning lines extending in a row direction, and lead-out lines extending in the column direction. Each of the lead-out lines intersects with corresponding one of the scanning lines at an intersection and is electrically coupled to the corresponding one of the scanning lines at a node. The node is disposed at the intersection or in a region surrounding the intersection. The driving circuit supplies corresponding one of the signal lines with a signal pulse corresponding to an image signal, and supplies corresponding one of the lead-out lines with a selection pulse having a peak value based on a distance from one end of the corresponding one of the lead-out lines to the corresponding node, after increasing the peak value with an increase in the distance.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: January 28, 2020
    Assignee: JOLED INC.
    Inventors: Atsuhito Murai, Jiro Yamada, Yasuhiro Terai, Masahiko Kondo, Noriteru Maeda
  • Publication number: 20200027900
    Abstract: A thin-film transistor substrate includes a pixel circuit, an interlayer insulating film, electrodes, and a hard mask metal. The pixel circuit includes a thin film transistor. The interlayer insulating film has contact holes and covers the pixel circuit. The electrodes are exposed above a surface of the interlayer insulating film, and electrically coupled to the pixel circuit via the contact holes. The hard mask metal has openings at portions facing the contact holes and is provided on the surface of the interlayer insulating film.
    Type: Application
    Filed: June 7, 2019
    Publication date: January 23, 2020
    Inventors: Ryosuke EBIHARA, Yasuhiro TERAI, Atsuhito MURAI
  • Publication number: 20190348488
    Abstract: A display unit includes a substrate, a first electrode, a second electrode, an organic layer, and an auxiliary electrically-conductive layer. The substrate includes a pixel region including a plurality of pixels and a peripheral region outside the pixel region. The first electrode is provided for each of the plurality of pixels in the pixel region on the substrate. The second electrode is opposed to the first electrode, and is provided common for the plurality of pixels. The organic layer is provided between the second electrode and the first electrode, and includes a light-emitting layer. The auxiliary electrically-conductive layer includes an organic electrically-conductive material, and the auxiliary electrically-conductive layer is disposed in the pixel region on the substrate and is electrically coupled to the second electrode.
    Type: Application
    Filed: December 4, 2018
    Publication date: November 14, 2019
    Inventors: Yasuhiro TERAI, Yasuharu SHINOKAWA, Jiro YAMADA, Atsuhito MURAI, Masahiko KONDO, Noriteru MAEDA
  • Publication number: 20190318688
    Abstract: A display unit includes a display panel, a photochromic layer, and an ultraviolet absorption layer. The photochromic layer is configured to be colored by ultraviolet light and be decolored or color-faded by visible light. The display panel includes an image display surface with a plurality of pixels. The pixels are provided below the image display surface and each include an organic light-emitting layer.
    Type: Application
    Filed: January 10, 2019
    Publication date: October 17, 2019
    Inventors: Masahiko KONDO, Jiro YAMADA, Atsuhito MURAI, Yasuhiro TERAI, Noriteru MAEDA
  • Publication number: 20190229163
    Abstract: A display unit includes multiple pixels, a first electrode, a partition wall, a light emission layer, and a second electrode. The multiple pixels each have a light emission region and a non-light emission region along a first direction. The first electrode is provided in the light emission region in each of the multiple pixels. The partition wall is provided between each two of the pixels that are adjacent to each other in a second direction. The second direction intersects the first direction. The light emission layer covers the first electrode and is provided in the light emission region and the non-light emission region in a continuous manner. The second electrode faces the first electrode across the light emission layer.
    Type: Application
    Filed: December 5, 2018
    Publication date: July 25, 2019
    Inventors: Atsuhito MURAI, Jiro YAMADA, Yasuhiro TERAI, Masahiko KONDO, Noriteru MAEDA