Abstract: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.

Abstract: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.

Abstract: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.

Abstract: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.

Abstract: A semiconductor device has an electrical fuse formed on a substrate, having a first interconnect, a second interconnect respectively formed in different layers, and a via provided in a layer between the first interconnect and the second interconnect, connected to one end of the second interconnect and connected also to the first interconnect; and a guard interconnect portion formed in the same layer with the second interconnect, so as to surround such one end of the second interconnect, wherein, in a plan view, the second interconnect is formed so as to extend from the other end towards such one end, and the guard interconnect portion is formed so as to surround such one end of the second interconnect in three directions, while placing such one end at the center thereof.

Abstract: The relationship between the difference between design and measured values of the gate length of a gate electrode of a transistor and the dose of an impurity to be injected into SD extension regions or pocket regions which is necessary to equalize characteristics of the transistor to design values is formulated. The gate length of the gate electrode which is produced by photolithography and etching process is measured. The dose of the impurity to be injected into the SD extension regions or the pocket regions is adjusted to bring deviations of the characteristics of the transistor from the design values into a predetermined range, based on the measured value of the gate length and the formulated relationship.

Abstract: A method for forming a MOSFET includes the steps of forming cobalt silicide layers on a polysilicon gate electrode and source/drain regions, implanting impurity ions to form source/drain extensions and diffusing the impurity ions in the source/drain extensions The temperature of the heat treatment for diffusing step is lower than the maximum of the temperatures of the heat treatment for forming the silicide layer, whereby a MOSFET having excellent short-channel characteristics and a higher reliability can be obtained.

Abstract: An n-channel type field effect transistor and a p-channel type field effect transistor are fabricated on a p-type well and an n-type well, respectively, and the arsenic-doped gate electrode of the n-channel type field effect transistor is thinner than the boron-doped gate electrode of the p-channel type field effect transistor so that the arsenic and the boron are appropriately diffused in the gate electrodes during a rapid annealing.

Abstract: (issue) It is an issue to suppress variation in threshold voltage due to deterioration in shot channel characteristics and improve the slow trap characteristics of the MOS transistor for suppressing variation in threshold voltage of the transistor for a long-term use. (means for solving the issue) fluorine ions are implanted into a surface of a silicon substrate 1 but a peripheral region of a gate electrode on a p-MOS formation region. A first heat treatment is carried out for removing inter-lattice silicon atoms generated upon ion-implantation. Thereafter, a second heat treatment is carried out for diffusing fluorine ions into a region directly under the gate electrode. The first heat treatment is a lamp anneal such as RTA, and the second heat treatment is a furnace anneal.

Abstract: A section separator region is formed in a semiconductor substrate in which a p-type well region has been formed, to separate the substrate into an I/O section and a core section. An oxide film and a plysilicon film are form at the I/O section, and pre-formation treatment is carried out. Then, an oxide film is formed over the exposed surface by the thermal oxidization. A metal film is formed on the oxide film. The metal film on the I/O section is moved. The polysilicon film and the metal film are patterned to be gate electrodes. Then, ion implantation is carried out to implant impurity into the exposed surface to form source/drain regions corresponding to the gate electrodes respectively.

Abstract: A MOS transistor fabrication method of the present invention comprises a step of forming a gate insulating film upon a semiconductor substrate; a step of forming a silicon film made from polysilicon or amorphous silicon upon the gate insulating film; a step of applying a heat treatment carried out at 800 to 1000° C. and for a duration of 1 to 10 seconds on the silicon film; a step of pre-doping by implanting impurity ions into the silicon film; a step of patterning a gate electrode by etching the silicon film; a step of forming sidewalls at the side portions of the gate electrode; and a step of doping the gate electrode with an impurity by implanting ions into the gate electrode and the semiconductor substrate as well as forming a source and a drain on the surface of the semiconductor substrate.

Abstract: A method is disclosed for fabricating a semiconductor integrated circuit device in which first pMOS transistors having a gate insulation film composed of a silicon oxide film are mounted together with second pMOS transistors having a gate insulation film composed of a silicon oxide-nitride film that is thinner than the silicon oxide film; wherein an impurity is implanted in advance in a polysilicon layer that is grown on the surfaces of the silicon oxide film and the silicon oxide-nitride film in only those positions at which second pMOS transistors are to be formed before patterning the polysilicon layer into gate electrodes. The polysilicon layer is then patterned to form gate electrodes, following which the gate electrodes and silicon substrate are each implanted with impurity to form source-drain regions.

Abstract: A process for preparing a semiconductor which is capable of implanting indium effectively during the process of forming a gate insulation film with different levels of thickness includes a 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed thereon to form a P-well region before forming a 1st N-channel region made of components other than indium on the P-well region, a 2nd step of removing the 1st resist mask before forming a 1st gate insulation film on the surface of the substrate, a 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the 1st gate insulation film, and removing partially the 1st gate insulation film, a 4th step of forming a P-well region inside the 1st gate insulation film partially removed region before forming a 2nd N-channel region containing indium on this P-well region, and a 5th step of removing the 2nd resist mask before forming a 2nd gat

Abstract: A process for preparing a semiconductor which is capable of implanting indium effectively during the process of forming a gate insulation film with different levels of thickness includes a 1st step of forming a 1st resist mask on a predetermined region lying on a P-type silicon substrate having an element isolation region formed thereon to form a P-well region before forming a 1st N-channel region made of components other than indium on the P-well region, a 2nd step of removing the 1st resist mask before forming a 1st gate insulation film on the surface of the substrate, a 3rd step of forming a 2nd resist mask on the predetermined region except the 1st N-channel region after forming the 1st gate insulation film, and removing partially the 1st gate insulation film, a 4th step of forming a P-well region inside the 1st gate insulation film partially removed region before forming a 2nd N-channel region containing indium on this P-well region, and a 5th step of removing the 2nd resist mask before forming a 2nd gat

Abstract: The relationship between the difference between design and measured values of the gate length of a gate electrode of a transistor and the dose of an impurity to be injected into SD extension regions or pocket regions which is necessary to equalize characteristics of the transistor to design values is formulated. The gate length of the gate electrode which is produced by photolithography and etching process is measured. The dose of the impurity to be injected into the SD extension regions or the pocket regions is adjusted to bring deviations of the characteristics of the transistor from the design values into a predetermined range, based on the measured value of the gate length and the formulated relationship.

Abstract: In manufacturing a MOS field effect transistor having a gate oxide film with a thickness of 3 nm or less, a deposition treatment or the like is performed under the condition that the substrate temperature is 650 to 770° C., and thereafter an annealing treatment is carried out under the condition that the substrate temperature is 900 to 1100° C.

Abstract: After a source-drain region is formed, fluorine 24 is ion-implanted into the entire surface of a substrate and thereafter a heat treatment is conducted, for example, at 600 to 800° C. Through this heat treatment, the dangling binds and the Si—H bonds in the channel regions 26 are substituted by the Si—F bonds, which prevents the generation of the negative bias temperature instability effect in a MOSFET.

Abstract: An n-channel type field effect transistor and a p-channel type field effect transistor are fabricated on a p-type well and an n-type well, respectively, and the arsenic-doped gate electrode of the n-channel type field effect transistor is thinner than the boron-doped gate electrode of the p-channel type field effect transistor so that the arsenic and the boron are appropriately diffused in the gate electrodes during a rapid annealing.

Abstract: A method of manufacturing a semiconductor device includes the step of forming a gate electrode on a semiconductor substrate via a gate insulating film and the step of forming a first insulating film on side surfaces of the gate electrode and an upper surface of the semiconductor substrate. Also the method includes the step of forming a second insulating film on the first insulating film and the step of etching back the first and second insulating films to form side walls of the gate electrode each of which includes layers of the first and second insulating films. The method includes the step of etching the first insulating films of the side walls to remain a part of the first insulating film layers.

Abstract: A side-wall film of a gate electrode is fabricated as a two-layer structure including an underlying thin silicon nitride film and a relatively thick silicon oxide film. The silicon nitride film covers and protects the edge of the gate oxide film against formation of a gate bird's beak at the edge of the gate oxide film. The side-wall contacts with the silicon substrate substantially at the thick silicon oxide film of the side-wall, which prevents formation of a carrier trap area adjacent to the channel area. The bottom of the side-wall may be a nitride-doped silicon oxide instead.