Abstract: A phase adjusting circuit for adjusting a phase of each bit of serial data by synchronizing with a system clock. The phase adjusting circuit includes a plurality of registers. Each bit of data is input into a corresponding one of the plurality of registers in a predetermined cyclic order, synchronized with a receiving clock which is extracted from the data, and outputting outputs of the registers in parallel. The outputs are each selected in a selector circuit under a control of the selector control signal in the same order as the above input to the registers. The selector control signal is generated by detecting a phase relationship between phases of the receiving clock and the system clock, and generating a selector control signal having a phase which is determined according to the phase relationship. Then, each bit of the above selected output is synchronized with the system clock.

Abstract: A reception processing unit receives digital data in successive data frames, each frame comprising a supervisory data field and an associated information data field and, further, a negative stuff or a positive stuff in accordance with need, and detects the head position of the information data field. An enable signal is produced only during and throughout a time interval in which the information data field appears in each successive, received data frame; a count operation of a counter is performed only during the interval of the enable signal. The head position is detected each time the counter finishes counting a number of bytes equal to the fixed length of the information data field.

Abstract: Disclosed is a drop/insert processing circuit connected to, for example, a broadband subscriber network including a high speed data loop. The circuit is formed in one body comprising a single shift register, a single clock signal generator, a low speed data insertion control circuit, and a low speed data dropping circuit, whereby the circuit scale is reduced and the control is simplified.