Patents by Inventor Atsuko Miyashita

Atsuko Miyashita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6421511
    Abstract: A transfer device for transferring a toner image formed on an image carrier onto a transfer material conveyed on a transfer belt. The transfer device includes a cleaning member having a dielectric surface layer for cleaning a surface of the transfer belt, and a bias application unit for applying to the cleaning member a cleaning bias having an opposite polarity to an electric charge polarity of a toner forming the toner image. Further, specific characteristic values of the dielectric surface layer are set to achieve a higher than predetermined cleaning level, such as setting a volume resistivity of the dielectric surface layer is set to 1E4 ohms/square or more.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: July 16, 2002
    Assignee: Ricoh Company, Ltd.
    Inventors: Toshihiro Sugiyama, Hiroshi Ishii, Hiroshi Saitoh, Atsuko Miyashita
  • Publication number: 20010002956
    Abstract: A transfer device comprises a cleaning roller that has a dielectric layer on its surface and cleans the surface of a transfer belt, and transfers a toner image formed on a photosensitive drum onto transfer paper on the transfer belt. A power supply, which applies a cleaning bias of the opposite polarity to an electric charge polarity of the toner that forms a toner image, is provided, and volume resistivity of the dielectric layer is set to 1E3 ohm-cm or more. By specifying characteristic values of the dielectric layer provided on the surface of the cleaning member, the cleaning effect of the dielectric layer can be maintained higher than a predetermined level and the transfer belt can effectively be cleaned.
    Type: Application
    Filed: December 1, 2000
    Publication date: June 7, 2001
    Inventors: Toshihiro Sugiyama, Hiroshi Ishii, Hiroshi Saitoh, Atsuko Miyashita
  • Patent number: 5698878
    Abstract: A DRAM cell includes first and second trenches formed in a P-type silicon substrate, a first N-type diffusion layer formed around the first trench, and a second N-type diffusion layer formed around the second trench, contacting the first N-type diffusion layer, and reaching the surface of the substrate. In the first trench, a storage node electrode whose capacitance is coupled to the first N-type diffusion layer and a conductive polysilicon film for leading the storage node electrode to the surface of the substrate are provided. One of source and drain regions of each cell transistor is connected to the conductive polysilicon film. The first N-type diffusion layer is connected to the second N-type diffusion layer, and the second diffusion layer is connected to a plate potential supply-line.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: December 16, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Miyashita, Yusuke Kohyama