Patents by Inventor Atsuko Monma
Atsuko Monma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8164371Abstract: To provide a duty detection circuit including: a plurality of duty detectors that detect a duty ratio of internal clocks; a controller that controls the plurality of duty detectors so that the plurality of duty detectors operates in different phases from one another; and an output selecting unit that selects one of duty detection signals from the plurality of duty detectors. According to the present invention, since the duty detectors operate in the different phases from one another, the output selecting unit can output a duty detection signal with a higher frequency than a generation frequency with which each duty detector generates the duty detection signal. Accordingly, when the duty detection circuit according to the present invention is used to adjust a clock of the DLL circuit, a control period of the DLL circuit can be reduced.Type: GrantFiled: March 12, 2010Date of Patent: April 24, 2012Assignee: Elpida Memory, Inc.Inventor: Atsuko Monma
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Publication number: 20110204942Abstract: A clock control circuit includes: a phase determination circuit that generates a phase determination signal based on a phase of an external clock signal; a counter circuit having a count value updated based on a logic level of the phase determination signal; a delay line that generates an internal clock signal by delaying the external clock signal based on the count value; and a pitch adjustment circuit that sets an update pitch of the counter circuit to be twice as high as a minimum pitch in a period in which the phase determination signal has no change, and sets the update pitch of the counter circuit to the minimum pitch in response to a change in the phase determination signal. With this configuration, it is possible to realize quick and highly accurate locking of a DLL circuit.Type: ApplicationFiled: February 23, 2011Publication date: August 25, 2011Applicant: Elpida Memory, Inc.Inventors: Tsuneo Abe, Atsuko Monma
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Publication number: 20100237917Abstract: To provide a duty detection circuit including: a plurality of duty detectors that detect a duty ratio of internal clocks; a controller that controls the plurality of duty detectors so that the plurality of duty detectors operates in different phases from one another; and an output selecting unit that selects one of duty detection signals from the plurality of duty detectors. According to the present invention, since the duty detectors operate in the different phases from one another, the output selecting unit can output a duty detection signal with a higher frequency than a generation frequency with which each duty detector generates the duty detection signal. Accordingly, when the duty detection circuit according to the present invention is used to adjust a clock of the DLL circuit, a control period of the DLL circuit can be reduced.Type: ApplicationFiled: March 12, 2010Publication date: September 23, 2010Applicant: ELPIDA MEMORY, INC.Inventor: Atsuko Monma
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Patent number: 7642829Abstract: A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an amplifier for amplifying the output of the integration circuit; a latch circuit for latching the output of the amplifier; a control circuit for controlling the operation timings of each component; a bias circuit for feeding a BIAS signal to the integration circuit; and a frequency monitor circuit unit for monitoring the frequency of the clock signal. The frequency monitor circuit unit is a circuit component used when the power source is turned on, during resetting, and when other initial settings are performed, and detects the actual frequency of the clock signal and adjusts the amount of charging or discharging of the capacitors C1 through C4 in the integration circuit according to this actual frequency.Type: GrantFiled: January 29, 2008Date of Patent: January 5, 2010Assignee: Elpida Memory, Inc.Inventors: Atsuko Monma, Kanji Oishi
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Patent number: 7411435Abstract: A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an amplifier for amplifying the output of the integration circuit; a latch circuit for latching the output of the amplifier; a control circuit for controlling the operation timings of each component; a bias circuit for feeding a BIAS signal to the integration circuit; and a frequency monitor circuit unit for monitoring the frequency of the clock signal. The frequency monitor circuit unit is a circuit component used when the power source is turned on, during resetting, and when other initial settings are performed, and detects the actual frequency of the clock signal and adjusts the amount of charging or discharging of the capacitors C1 through C4 in the integration circuit according to this actual frequency.Type: GrantFiled: February 3, 2006Date of Patent: August 12, 2008Assignee: Elpida Memory, Inc.Inventors: Atsuko Monma, Kanji Oishi
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Publication number: 20080129358Abstract: A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an amplifier for amplifying the output of the integration circuit; a latch circuit for latching the output of the amplifier; a control circuit for controlling the operation timings of each component; a bias circuit for feeding a BIAS signal to the integration circuit; and a frequency monitor circuit unit for monitoring the frequency of the clock signal. The frequency monitor circuit unit is a circuit component used when the power source is turned on, during resetting, and when other initial settings are performed, and detects the actual frequency of the clock signal and adjusts the amount of charging or discharging of the capacitors C1 through C4 in the integration circuit according to this actual frequency.Type: ApplicationFiled: January 29, 2008Publication date: June 5, 2008Applicant: ELPIDA MEMORY, INC.Inventors: Atsuko Monma, Kanji Oishi
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Patent number: 7276950Abstract: The clock delay circuit according to the present invention includes a delay circuit section, a selection circuit section, and jitter suppression elements. The delay circuit section provides a plurality of delay clock signals that are obtained by delaying a clock signal with a different delay amount. The selection circuit section selects and provides any one of a plurality of delay clock signals that are provided from the delay circuit section. The jitter suppression elements are connected in series between the delay circuit section and the selection circuit section. When jitters occur at the time of switching the delay clock signals at the selection circuit section, the jitter suppression elements serve to prevent the propagation of the jitters through the delay circuit section.Type: GrantFiled: October 20, 2005Date of Patent: October 2, 2007Assignee: Elpida Memory, Inc.Inventors: Atsuko Monma, Kanji Oishi
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Publication number: 20060170475Abstract: The duty detection circuit (100) comprises an integration circuit (110) for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels (DB signal and VREF signal) in accordance with the duty ratio of these internal clock signals; an amplifier (120) for amplifying the output of the integration circuit (110); a latch circuit (130) for latching the output of the amplifier (120); a control circuit (140) for controlling the operation timings of each component; a bias circuit (150) for feeding a BIAS signal to the integration circuit (110); and a frequency monitor circuit unit (160) for monitoring the frequency of the clock signal.Type: ApplicationFiled: February 3, 2006Publication date: August 3, 2006Inventors: Atsuko Monma, Kanji Oishi
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Publication number: 20060091926Abstract: The clock delay circuit according to the present invention includes a delay circuit section, a selection circuit section, and jitter suppression elements. The delay circuit section provides a plurality of delay clock signals that are obtained by delaying a clock signal with a different delay amount. The selection circuit section selects and provides any one of a plurality of delay clock signals that are provided from the delay circuit section. The jitter suppression elements are connected in series between the delay circuit section and the selection circuit section. When jitters occur at the time of switching the delay clock signals at the selection circuit section, the jitter suppression elements serve to prevent the propagation of the jitters through the delay circuit section.Type: ApplicationFiled: October 20, 2005Publication date: May 4, 2006Inventors: Atsuko Monma, Kanj Oishi
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Patent number: RE46231Abstract: To provide a duty detection circuit including: a plurality of duty detectors that detect a duty ratio of internal clocks; a controller that controls the plurality of duty detectors so that the plurality of duty detectors operates in different phases from one another; and an output selecting unit that selects one of duty detection signals from the plurality of duty detectors. According to the present invention, since the duty detectors operate in the different phases from one another, the output selecting unit can output a duty detection signal with a higher frequency than a generation frequency with which each duty detector generates the duty detection signal. Accordingly, when the duty detection circuit according to the present invention is used to adjust a clock of the DLL circuit, a control period of the DLL circuit can be reduced.Type: GrantFiled: April 18, 2014Date of Patent: December 6, 2016Assignee: LONGITUDE SEMICONDUCTOR S.A.R.L.Inventor: Atsuko Monma