Abstract: A battery includes a battery element, a housing body, and a valve device. The housing body houses the battery element. The valve device is in communication with the inside of the housing body. Heat-sealable resin layers face each other in a peripheral edge portion of the housing body. A joined edge portion in which the mutually facing heat-sealable resin layers are fused together is formed in the peripheral edge portion of the housing body. The valve device is configured to reduce an internal pressure of the housing body if the internal pressure is increased due to gas generated in the housing body. The valve device includes a first portion that is located on an outer side of an edge of the joined edge portion and a second portion that is sandwiched between the heat-sealable resin layers in the joined edge portion.

Abstract: A battery includes a battery element, a housing body, and a valve device. The housing body is constituted by at least one laminate including at least a base material layer, a barrier layer, and a heat-sealable resin layer layered in that order and houses the battery element. The valve device is in communication with the inside of the housing body. A joined edge portion in which the mutually facing heat-sealable resin layers are fused together is formed in a peripheral edge portion of the housing body. The valve device includes a first portion and a second portion. A valve mechanism configured to reduce the internal pressure of the housing body if the internal pressure is increased due to gas generated in the housing body is formed in the first portion. An air passage configured to guide gas generated in the housing body toward the valve mechanism is formed in the second portion. The first portion is located on an outer side of an edge of the joined edge portion.

Abstract: A packaging material for batteries including a laminate in which at least a base material layer, a metal layer, and a sealant layer are laminated in order. The battery packaging material satisfies the relationships of: (A1?A2)?60 N/15 mm; and (B1?B2)?50 N/15 mm. A1 is a stress in elongation by 10% in the MD direction and B1 is a stress in elongation by 10% in the TD direction in the laminate, and A2 is a stress in elongation by 10% in the MD direction and B2 is a stress in elongation by 10% in the TD direction in the base material layer.

Abstract: A semiconductor device includes first, second, third, and fourth electrodes, a first insulating film, and first, second third, and fourth silicon carbide layers. A first distance between the first electrode and a first interface between the fourth electrode and fourth silicon carbide region is longer than a second distance between the first insulating film and a second interface between the third silicon carbide region and the fourth silicon carbide region. The fourth silicon carbide region is between the third silicon carbide region and the second silicon carbide region in a direction perendicular to the second interface.

Abstract: A semiconductor device according to an embodiment includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC layer provided on the SiC substrate, having a first surface, and having a lower first-conductivity-type impurity concentration than the SiC substrate, first second-conductivity-type SiC regions provided in the first surface of the SiC layer, second second-conductivity-type SiC regions provided in the first SiC regions and having a higher second-conductivity-type impurity concentration than the first SiC region, silicide layers provided on the second SiC regions and having a second surface, a difference between a distance from the SiC substrate to the second surface and a distance from the SiC substrate to the first surface being equal to or less than 0.2 ?m, a first electrode provided to contact with the SiC layer and the silicide layers, and a second electrode provided to contact with the SiC substrate.

Abstract: Provided is a semiconductor device according to an embodiment including: a first electrode; a second electrode; a third electrode provided between the first electrode and the second electrode; a first insulating film provided between the third electrode and the second electrode; a silicon carbide layer provided between the first insulating film and the second electrode; a first silicon carbide region provided between the third electrode and the second electrode, the first silicon carbide region being provided in the silicon carbide layer; a second silicon carbide region provided between the third electrode and the first silicon carbide region, the second silicon carbide region being provided in the silicon carbide layer; a third silicon carbide region provided between the third electrode and the second silicon carbide region, the third.

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first electrode on the first surface, a second electrode on the second surface, a first semiconductor region of a first conductivity type in the semiconductor layer, a second semiconductor region of a second conductivity type in an element region of the semiconductor layer between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the second semiconductor region and the first electrode, and a fourth semiconductor region of the second conductivity type in a termination region of the semiconductor layer inwardly of the first surface. A distance between the fourth semiconductor region and the second surface is greater than a distance between the second semiconductor region and the second surface.

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface, a first electrode on the first surface, a second electrode on the second surface, a first semiconductor region of a first conductivity type in the semiconductor layer, a second semiconductor region of a second conductivity type in an element region of the semiconductor layer between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the second semiconductor region and the first electrode, and a fourth semiconductor region of the second conductivity type in a termination region of the semiconductor layer inwardly of the first surface. A distance between the fourth semiconductor region and the second surface is greater than a distance between the second semiconductor region and the second surface.

Abstract: A semiconductor device according to an embodiment includes a first-conductivity-type SiC substrate, a first-conductivity-type SiC layer provided on the SiC substrate, having a first surface, and having a lower first-conductivity-type impurity concentration than the SiC substrate, first second-conductivity-type SiC regions provided in the first surface of the SiC layer, second second-conductivity-type SiC regions provided in the first SiC regions and having a higher second-conductivity-type impurity concentration than the first SiC region, silicide layers provided on the second SiC regions and having a second surface, a difference between a distance from the SiC substrate to the second surface and a distance from the SiC substrate to the first surface being equal to or less than 0.2 ?m, a first electrode provided to contact with the SiC layer and the silicide layers, and a second electrode provided to contact with the SiC substrate.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device, including: detecting whether or not a defect being present in a wafer substrate and obtaining coordinate information of the defect; and determining positions of a first disposal region and a second disposal region in a semiconductor chip region based on the coordinate information so that the defect falls in the first disposal region in disposing in a plane of the semiconductor chip region having the first disposal region on which a first diode having a first conductivity type region and a second conductivity type region being disposed and the second disposal region on which a second diode having a metal film and a semiconductor region contacting the metal film being disposed.

Abstract: A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.

Abstract: A manufacturing method for a semiconductor device includes implanting dopants into a silicon carbide substrate, applying a carbon-containing material on at least one surface of the silicon carbide substrate, and heating the silicon carbide substrate having the carbon-containing material applied thereon to form a carbon layer on surfaces of the silicon carbide substrate. The heating is performed in a non-oxidizing atmosphere, and is followed by another heating step for activating the dopants.

Abstract: A semiconductor device of an embodiment includes a first conductive type silicon carbide substrate having first and second main surfaces, a first conductive type silicon carbide layer formed on the first main surface, a second conductive type first silicon carbide region formed in the silicon carbide layer, and a first conductive type second silicon carbide region formed in the first silicon carbide region. The device includes a trench penetrating through the first and second silicon carbide regions, and a second conductive type third silicon carbide region formed on a bottom and a side surface of the trench. The third silicon carbide region is in contact with the first silicon carbide region, and is formed between the trench and the silicon carbide layer. In addition, the device includes a gate insulating film formed in the trench, a gate electrode, a first electrode, and a second electrode.

Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.

Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.

Abstract: A solid-state imaging device includes: a substrate; a photo-receiving portion formed in the substrate; a wiring layer formed on the substrate and having a trench being formed on a region directly above the photo-receiving portion; and a light guiding member provided in the trench and made of organic material. An empty space is formed between a side wall of the trench and a side surface of the light guiding member. The side surface of the light guiding member is curved so that a central part of the side surface along a vertical direction is closer to a center axis of the trench than both end parts of the side surface along the vertical direction.

Abstract: A first semiconductor pillar layer of a first conductivity type is formed on a main surface of a semiconductor substrate of the first conductivity type. A second semiconductor pillar layer of a second conductivity type is formed adjacent to the first semiconductor pillar layer. A third semiconductor pillar layer of the first conductivity type is formed adjacent to the second semiconductor pillar layer. A semiconductor base layer of the second conductivity type is formed on the main surface of the second semiconductor pillar layer. An insulated-gate type semiconductor element is formed in the semiconductor base layer. The carrier concentration on the side of a main surface of each of said first through third semiconductor pillar layers is higher than a carrier concentration on the opposite side of said main surface in each of said first through third semiconductor pillar layers.

Abstract: The semiconductor comprises a channel layer including GaN, a barrier layer formed by laminating a first layer including AlXGa1-XN (0.05?X?0.25) and a second layer including AlYGa1-YN (0.20?Y?0.28, X<Y), source and drain electrodes provided spaced apart from each other on the barrier layer, and a gate electrode provided on the bottom of a ditch extending between the source and drain electrodes and formed with a depth starting from the top surface of the barrier layer reaching the first layer adjacent to the channel layer.

Abstract: Provided is a semiconductor device including a semiconductor substrate which includes a first semiconductor layer of a first conductivity and a pair of second semiconductor layers disposed on the first semiconductor layer and spaced apart from each other to form a trench therebetween, wherein the second semiconductor layer includes a first impurity-diffused region of the first conductivity extending from a lower surface toward an upper surface of the second semiconductor layer, and a second impurity-diffused region of a second conductivity which extends from the lower surface toward the upper surface and is adjacent to the first impurity-diffused region, an insulating layer covering a sidewall of the trench, and a cap layer which is in contact with the semiconductor substrate and covers an opening of the trench to form an enclosed space in the trench, a material of the cap layer being almost the same as that of the semiconductor substrate.

Abstract: A solid-state imaging device includes: a substrate; a photo-receiving portion formed in the substrate; a wiring layer formed on the substrate and having a trench being formed on a region directly above the photo-receiving portion; and a light guiding member provided in the trench and made of organic material. An empty space is formed between a side wall of the trench and a side surface of the light guiding member. The side surface of the light guiding member is curved so that a central part of the side surface along a vertical direction is closer to a center axis of the trench than both end parts of the side surface along the vertical direction.