Patents by Inventor Atsunobu OKAZAKI

Atsunobu OKAZAKI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11349449
    Abstract: Provided is a laminated electronic component in which defective formation is unlikely to cause in a shield conductor layer on a side surface of a laminate. The laminated electronic component includes a laminate 1, in which substrate layers 1a to 1i are laminated, having an outer surface including a first main surface 1B, a second main surface 1T, and a side surface 1S, internal electrodes (a ground electrode 2, coil electrodes 3, capacitor electrodes 4, and wiring electrodes 5), an external electrode 7, and a first plating layer 9 formed on a surface of the external electrode 7.
    Type: Grant
    Filed: January 8, 2021
    Date of Patent: May 31, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Issei Yamamoto, Atsunobu Okazaki, Yuki Asano
  • Publication number: 20210126608
    Abstract: Provided is a laminated electronic component in which defective formation is unlikely to cause in a shield conductor layer on a side surface of a laminate. The laminated electronic component includes a laminate 1, in which substrate layers 1a to 1i are laminated, having an outer surface including a first main surface 1B, a second main surface 1T, and a side surface 1S, internal electrodes (a ground electrode 2, coil electrodes 3, capacitor electrodes 4, and wiring electrodes 5), an external electrode 7, and a first plating layer 9 formed on a surface of the external electrode 7.
    Type: Application
    Filed: January 8, 2021
    Publication date: April 29, 2021
    Inventors: Issei YAMAMOTO, Atsunobu OKAZAKI, Yuki ASANO