Patents by Inventor Atsunobu Suzuki

Atsunobu Suzuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8288865
    Abstract: A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: October 16, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Atsunobu Suzuki, Koichi Saito, Yasuyuki Yanase, Takahiro Fujii
  • Patent number: 8274148
    Abstract: A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.
    Type: Grant
    Filed: March 19, 2010
    Date of Patent: September 25, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasuyuki Yanase, Atsunobu Suzuki, Yoshio Okayama
  • Patent number: 8242598
    Abstract: A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: August 14, 2012
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Atsunobu Suzuki, Koichi Saito, Yasuyuki Yanase, Takahiro Fujii
  • Publication number: 20100276800
    Abstract: A first circuit element and a second element are mounted with their electrode forming surfaces facing a wiring layer. A first bump electrode formed integrally with the wiring layer on one face substantially penetrates a first insulating resin layer. A gold plating layer covering an element electrode of the first circuit element and a gold plating layer disposed on top of the first bump electrode are bonded together by Au—Au bonding. A second bump electrode formed integrally with the wiring layer on one face substantially penetrates the first and the second insulating resin layer. A gold plating layer covering an element electrode of the second circuit element and a gold plating layer disposed on top of the second bump electrode are bonded together by Au—Au bonding.
    Type: Application
    Filed: March 19, 2010
    Publication date: November 4, 2010
    Inventors: Yasuyuki YANASE, Atsunobu Suzuki, Yoshio Okayama
  • Publication number: 20100193946
    Abstract: A semiconductor module includes: an insulating resin layer; a wiring layer which is provided on one main surface of the insulating resin layer and which includes an external connection region; bump electrodes which are electrically connected to the wiring layer and each of which is formed such that it protrudes from the wiring layer toward the insulating resin layer; a semiconductor device which is provided on the other main surface of the insulating resin layer and which includes device electrodes connected to the bump electrode; and a wiring protection layer provided on the wiring layer and the insulating resin layer so as to expose the external connection region. In the semiconductor module, the outer edge portion of the wiring protection layer is in contact with the external edge portion of the semiconductor device such that it shields at least a part of the semiconductor resin layer at the side edge.
    Type: Application
    Filed: January 29, 2010
    Publication date: August 5, 2010
    Inventors: Atsunobu Suzuki, Koichi Saito, Yasuyuki Yanase, Takahiro Fujii