Patents by Inventor Atsunori Tanaka

Atsunori Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240068200
    Abstract: A work machine comprises a joystick to control a movement of the work machine, a lock lever to control a hydraulic system of the work machine, a display to output information to an operator inside the work machine, and processing circuitry. The processing circuitry is configured to lock the hydraulic system without receiving an input from the lock lever, perform an idling stop operation of an engine of the work machine, output, on the display, an instruction for the operator to operate the joystick to restart the engine of the work machine, detect a predetermined operation of the joystick, perform an engine restart operation, under a condition that the predetermined operation of the joystick is detected, and unlock the hydraulic system without receiving the input from the lock lever.
    Type: Application
    Filed: August 26, 2022
    Publication date: February 29, 2024
    Applicant: Caterpillar SARL
    Inventors: Kensuke TANAKA, Atsunori SHIMAMOTO, Takashi KOTERA
  • Publication number: 20230197840
    Abstract: In one embodiment, a transistor includes a substrate, a buffer layer on the substrate a channel layer on the buffer layer, and one or more polarization layers on the channel layer. The one or more polarization layers include a group III-N material comprising a first group III constituent and a second group III constituent. The transistor further includes a plurality of p-type doped layers on the one or more polarization layers. Each of the plurality of p-type doped layers includes a first p-type dopant and the III-N material, wherein each successive layer of the first p-type doped layers has a lower proportion of the first group III constituent to the second group III constituent relative to a layer below it. The transistor also includes a p-type doped layer on the plurality of p-type doped layers comprising a second p-type dopant and a group III-N material.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Sanyam Bajaj, Michael S. Beumer, Robert Ehlert, Gregory P. McNerney, Nicholas Minutillo, Xiaoye Qin, Johann C. Rode, Atsunori Tanaka, Suresh Vishwanath, Patrick M. Wallace
  • Publication number: 20230132548
    Abstract: In one embodiment, a transistor is formed by a process comprising forming a buffer layer on a substrate, the buffer layer comprising a first group III-nitride (III-N) material (e.g., AlGaN), forming a channel layer on the buffer layer, the channel layer comprising a second III-N material (e.g., GaN), forming a polarization layer on the channel layer, the polarization layer comprising a third III-N material (e.g., AlGaN), flowing a p-type dopant precursor compound (e.g., Cp2Mg) after forming the polarization layer, forming a p-type doped layer (e.g., p-GaN) on the polarization layer, the p-type doped layer comprising a p-type dopant (e.g., Mg) and a fourth III-N material (e.g., GaN), forming a source region adjacent one end of the channel layer, and forming a drain region adjacent another end of the channel layer.
    Type: Application
    Filed: November 4, 2021
    Publication date: May 4, 2023
    Applicant: Intel Corporation
    Inventors: Atsunori Tanaka, Sanyam Bajaj, Michael S. Beumer, Robert Ehlert, Gregory P. McNerney, Nicholas Minutillo, Johann C. Rode, Suresh Vishwanath, Patrick M. Wallace
  • Patent number: 11363979
    Abstract: A nanowire probe sensor array including a substrate with a metal pattern thereon. An array of semiconductor vertical nanowire probes extends away from the substrate, and at least some of probes, and preferably all, are individually electrically addressed through the metal pattern. The metal pattern is insulated with dielectric, and base and stem portions of the nanowires are also preferably insulated. A fabrication process patterns metal connections on a substrate. A semiconductor substrate is bonded to the metal pattern. The semiconductor substrate is etched to form the neural nanowire probes that are bonded to the metal pattern. Dielectric is then deposited to insulate the metal pattern.
    Type: Grant
    Filed: January 19, 2017
    Date of Patent: June 21, 2022
    Assignee: The Regents of the University of California
    Inventors: Shadi A. Dayeh, Renjie Chen, Sang Heon Lee, Ren Liu, Yun Goo Ro, Atsunori Tanaka, Yoontae Hwang
  • Patent number: 11233142
    Abstract: Devices and methods of the invention use a plurality of Fin structures and or combine a planar portion with Fin structures to compensate for the first derivative of transconductance, gm. In preferred methods and devices, Fins have a plurality of widths and are selected to lead to the separate turn-on voltage thresholds for the largest, intermediate and smallest widths of the MIS HEMT fins flatten the transconductance gm curve over an operational range of gate source voltage.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 25, 2022
    Assignee: The Regents of the Unverslty of California
    Inventors: Shadi A. Dayeh, Woojin Choi, Renjie Chen, Atsunori Tanaka, Ren Liu
  • Patent number: 11056517
    Abstract: Methods and devices that monolithically integrate thin film elements/devices, e.g., environmental sensors, batteries and biosensors, with high performance integrated circuits, i.e., integrated circuits formed in a high quality device layer. Preferred embodiments further monolithically integrate a solar cell array. Preferred embodiments provide pin-size and integrated solar powered wearable electronic, ionic, molecular, radiation, etc. sensors and circuits.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: July 6, 2021
    Assignee: The Regents of the University of California
    Inventors: Shadi A. Dayeh, Yun Goo Ro, Namseok Park, Atsunori Tanaka, Siarhei Vishniakou, Ahmed Youssef, James Buckwalter, Cooper Levy
  • Publication number: 20200295170
    Abstract: Devices and methods of the invention use a plurality of Fin structures and or combine a planar portion with Fin structures to compensate for the first derivative of transconductance, gm. In preferred methods and devices, Fins have a plurality of widths and are selected to lead to the separate turn-on voltage thresholds for the largest, intermediate and smallest widths of the MIS HEMT fins flatten the transconductance gm curve over an operational range of gate source voltage.
    Type: Application
    Filed: October 31, 2018
    Publication date: September 17, 2020
    Inventors: Shadi A. Dayeh, Woojin Choi, Renjie Chen, Atsunori Tanaka, Ren Liu
  • Publication number: 20190021619
    Abstract: A nanowire probe sensor array including a substrate with a metal pattern thereon. An array of semiconductor vertical nanowire probes extends away from the substrate, and at least some of probes, and preferably all, are individually electrically addressed through the metal pattern. The metal pattern is insulated with dielectric, and base and stem portions of the nanowires are also preferably insulated. A fabrication process patterns metal connections on a substrate. A semiconductor substrate is bonded to the metal pattern. The semiconductor substrate is etched to form the neural nanowire probes that are bonded to the metal pattern. Dielectric is then deposited to insulate the metal pattern.
    Type: Application
    Filed: January 19, 2017
    Publication date: January 24, 2019
    Inventors: Shadi A. Dayeh, Renjie Chen, Sang Heon Lee, Ren Liu, Yun Goo Ro, Atsunori Tanaka, Yoontae Hwang
  • Publication number: 20180040649
    Abstract: Methods and devices that monolithically integrate thin film elements/devices, e.g., environmental sensors, batteries and biosensors, with high performance integrated circuits, i.e., integrated circuits formed in a high quality device layer. Preferred embodiments further monolithically integrate a solar cell array. Preferred embodiments provide pin-size and integrated solar powered wearable electronic, ionic, molecular, radiation, etc. sensors and circuits.
    Type: Application
    Filed: March 10, 2016
    Publication date: February 8, 2018
    Inventors: Shadi A. Dayeh, Yun Goo Ro, Namseok Park, Atsunori Tanaka, Siarhei Vishniakou, Ahmed Youssef, James Buckwalter, Cooper Levy