Patents by Inventor Atsuo Hatono

Atsuo Hatono has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7675455
    Abstract: A pulse radar is provided with a filter for eliminating a transmission waveform interfered with an answering signal from a received waveform, and a harmonic detector or a phase delay detector for detecting arrival and end of the answering signal reflected on a target.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: March 9, 2010
    Assignee: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Atsuo Hatono
  • Publication number: 20090051581
    Abstract: A pulse radar is provided with a filter for eliminating a transmission waveform interfered with an answering signal from a received waveform, and a harmonic detector or a phase delay detector for detecting arrival and end of the answering signal reflected on a target.
    Type: Application
    Filed: December 20, 2007
    Publication date: February 26, 2009
    Applicant: Fuji Jukogyo Kabushiki Kaisha
    Inventor: Atsuo Hatono
  • Publication number: 20020034163
    Abstract: A regulation apparatus for ATM cell delayvariation includes a variation regulating buffer for temporarily storing cells, a variation waiting timer for controlling a waiting time to read-out cells from the buffer, a read-out timer for controlling intervals at which cells are read from the buffer, a latest cell preservation memory for storing the latest cell transferred froma VPI/VCI and a selector for selecting a cell stored in the buffer to transfer the cell to a cell reproduction unit. The invention further includes a communication type discriminator for discriminating a communication type in a call set-up phase of a communication and for calculating a variation waiting time based on the discrimination to set the calculated variation waiting time to the variation waiting timer, and a dummy cell inserting circuit for inserting the last reaching cell as a dummy cell if a cell delay time cannot be regulated by the variation waiting time.
    Type: Application
    Filed: October 17, 2001
    Publication date: March 21, 2002
    Inventors: Shinichi Hamamoto, Masashi Hiraiwa, Atsuo Hatono
  • Patent number: 6335917
    Abstract: A regulation apparatus for ATM cell delay variation includes a variation regulating buffer for temporarily storing cells transferred thereto, a variation waiting timer for controlling a waiting time which extends from reception of the first cell to read-out of cells from the buffer, a read-out timer for controlling intervals at which cells are read from the buffer, a latest cell preservation memory for storing the latest cell transferred from a VPI/VCI demultiplexing unit and, a selector for selecting a cell stored in the buffer or in the memory to transfer the selected cell to a cell reproduction unit.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: January 1, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Hamamoto, Masashi Hiraiwa, Atsuo Hatono
  • Patent number: 5959991
    Abstract: A cell loss priority control method for an ATM switch in which degradation of the traffic characteristics of a high priority class or a low priority class is detected, a cell loss probability distribution in a buffer is estimated from the cell traffic characteristics, a buffer threshold value is obtained in accordance with the estimated cell loss probability distribution, and the cell is controlled by using the obtained buffer threshold value which maximizes total traffic throughput of both the high priority class and low priority class.
    Type: Grant
    Filed: October 16, 1996
    Date of Patent: September 28, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Hatono, Tadashi Tamaoki
  • Patent number: 5914936
    Abstract: An ATM exchange for performing the flow control adaptively in accordance with the seriousness of congestion, provided with a first threshold comparing circuit and a second threshold comparing circuit for comparing a cell queue length in a buffer of the exchange with a first and a second threshold, a timer counter which starts counting when the queue length exceeds the first threshold and is cleared to zero when the the queue length becomes smaller than the second threshold, a permissible time comparing circuit for comparing the count value with a permissible time, and a congestion counter for counting the output of the comparing circuit.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: June 22, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Hatono, Tatsuo Mochinaga
  • Patent number: 5774466
    Abstract: A regulation apparatus for ATM cell delay variation includes a variation regulating buffer for temporarily storing cells transferred thereto, a variation waiting timer for controlling a waiting time which extends from reception of the first cell to read-out of cells from the buffer, a read-out timer for controlling intervals at which cells are read from the buffer, a latest cell preservation memory for storing the latest cell transferred from a VPI/VCI demultiplexing unit and, a selector for selecting a cell stored in the buffer or in the memory to transfer the selected cell to a cell reproduction unit.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: June 30, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Shinichi Hamamoto, Masashi Hiraiwa, Atsuo Hatono
  • Patent number: 5737314
    Abstract: An ATM switch system having a traffic control function to reduce cell loss probability and delay of cells communicated through a network to be equal to or less than acceptable values, respectively. To achieve traffic control function, the invention provides a circuit to observe the queue of cells in the buffer, and an overflow testing circuit for obtaining a distribution of the queue size according to observed values of the queue and testing to decide, according to the distribution, whether an event has occurred that the cell loss probability is shifted due to the input cells to a distribution related to a cell loss probability exceeding an upper-limit value of acceptable cell loss probability.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: April 7, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Hatono, Masashi Hiraiwa
  • Patent number: 5699345
    Abstract: An ATM network includes a plurality of ATM-LANs which are connected through an ATM-WAN, when a source terminal and a destination terminal belong tb separate ATM-LANs connected through the ATM-WAN, the congestion control is performed as follows. When congestion occurs in an ATM-LAN in which the source terminal exists, the congestion control is performed by the BECN mechanism and when congestion occurs in an ATM-LAN other than the ATM-LAN in which the source terminal exists, the congestion control is performed by the FRP mechanism. When the source terminal and the destination terminal exist in the same ATM-LAN, the congestion control is performed by the FECN mechanism. Thus, in the ATM-LAN, cell loss can be suppressed upon occurrence of congestion.
    Type: Grant
    Filed: April 12, 1996
    Date of Patent: December 16, 1997
    Assignee: Hitachi, Ltd.
    Inventors: Tatsuya Watanuki, Atsushi Kimoto, Atsuo Hatono