Patents by Inventor Atsuo Isobe

Atsuo Isobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210074734
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Application
    Filed: October 29, 2020
    Publication date: March 11, 2021
    Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
  • Publication number: 20210040225
    Abstract: The present invention provides a pharmaceutical composition comprising an antibody which binds specifically to human TLR7 or monkey TLR7 and does not bind to mouse TLR7 or rat TLR7, and has an activity of inhibiting a function of human TLR7 or monkey TLR7, and the like.
    Type: Application
    Filed: October 13, 2020
    Publication date: February 11, 2021
    Applicants: Daiichi Sankyo Company, Limited, The University of Tokyo
    Inventors: Kensuke Miyake, Yusuke Murakami, Yuji Motoi, Atsuo Kanno, Toshiyuki Shimizu, Umeharu Ohto, Takaichi Shimozato, Atsushi Manno, Takashi Kagari, Jun Ishiguro, Kensuke Nakamura, Takashi Isobe
  • Patent number: 10910404
    Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: February 2, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinori Ieda, Atsuo Isobe, Yutaka Shionoiri, Tomoaki Atsumi
  • Patent number: 10910219
    Abstract: The present invention is characterized in that by laser beam being slantly incident to the convex lens, an aberration such as astigmatism or the like is occurred, and the shape of the laser beam is made linear on the irradiation surface or in its neighborhood. Since the present invention has a very simple configuration, the optical adjustment is easier, and the device becomes compact in size. Furthermore, since the beam is slantly incident with respect to the irradiated body, the return beam can be prevented.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: February 2, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Hidekazu Miyairi, Aiko Shiga, Akihisa Shimomura, Atsuo Isobe
  • Patent number: 10879272
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: December 29, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba
  • Patent number: 10825836
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: November 3, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Publication number: 20200250521
    Abstract: An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit.
    Type: Application
    Filed: August 28, 2018
    Publication date: August 6, 2020
    Inventors: Takahiko ISHIZU, Takayuki IKEDA, Atsuo ISOBE, Atsushi MIYAGUCHI, Shunpei YAMAZAKI
  • Publication number: 20200168635
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Application
    Filed: October 18, 2019
    Publication date: May 28, 2020
    Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
  • Publication number: 20200135770
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Atsuo ISOBE, Shunpei YAMAZAKI, Koji DAIRIKI, Hiroshi SHIBATA, Chiho KOKUBO, Tatsuya ARAO, Masahiko HAYAKAWA, Hidekazu MIYAIRI, Akihisa SHIMOMURA, Koichiro TANAKA, Mai AKIBA
  • Patent number: 10522689
    Abstract: It is an object to manufacture a semiconductor device in which a transistor including an oxide semiconductor has normally-off characteristics, small fluctuation in electric characteristics, and high reliability. First, first heat treatment is performed on a substrate, a base insulating layer is formed over the substrate, an oxide semiconductor layer is formed over the base insulating layer, and the step of performing the first heat treatment to the step of forming the oxide semiconductor layer are performed without exposure to the air. Next, after the oxide semiconductor layer is formed, second heat treatment is performed. An insulating layer from which oxygen is released by heating is used as the base insulating layer.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshinari Sasaki, Hitomi Sato, Kosei Noda, Yuta Endo, Mizuho Ikarashi, Keitaro Imai, Atsuo Isobe, Yutaka Okazaki
  • Patent number: 10515983
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: December 24, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba
  • Publication number: 20190348286
    Abstract: The present invention is characterized in that by laser beam being slantly incident to the convex lens, an aberration such as astigmatism or the like is occurred, and the shape of the laser beam is made linear on the irradiation surface or in its neighborhood. Since the present invention has a very simple configuration, the optical adjustment is easier, and the device becomes compact in size. Furthermore, since the beam is slantly incident with respect to the irradiated body, the return beam can be prevented.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 14, 2019
    Inventors: Koichiro TANAKA, Hidekazu MIYAIRI, Aiko SHIGA, Akihisa SHIMOMURA, Atsuo ISOBE
  • Publication number: 20190341404
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Application
    Filed: July 18, 2019
    Publication date: November 7, 2019
    Inventors: Atsuo ISOBE, Shunpei YAMAZAKI, Koji DAIRIKI, Hiroshi SHIBATA, Chiho KOKUBO, Tatsuya ARAO, Masahiko HAYAKAWA, Hidekazu MIYAIRI, Akihisa SHIMOMURA, Koichiro TANAKA, Mai AKIBA
  • Patent number: 10453863
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: October 22, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Wataru Uesugi, Hikaru Tamura, Atsuo Isobe
  • Patent number: 10388799
    Abstract: Stable electric characteristics and high reliability are provided to a miniaturized and integrated semiconductor device including an oxide semiconductor. In a transistor (a semiconductor device) including an oxide semiconductor film, the oxide semiconductor film is provided along a trench (groove) formed in an insulating layer. The trench includes a lower end corner portion having a curved shape with a curvature radius of longer than or equal to 20 nm and shorter than or equal to 60 nm, and the oxide semiconductor film is provided in contact with a bottom surface, the lower end corner portion, and an inner wall surface of the trench. The oxide semiconductor film includes a crystal having a c-axis substantially perpendicular to a surface at least over the lower end corner portion.
    Type: Grant
    Filed: February 28, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Toshinari Sasaki
  • Patent number: 10388670
    Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: August 20, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshinori Ieda, Atsuo Isobe, Yutaka Shionoiri, Tomoaki Atsumi
  • Patent number: 10366885
    Abstract: The present invention is characterized in that by laser beam being slantly incident to the convex lens, an aberration such as astigmatism or the like is occurred, and the shape of the laser beam is made linear on the irradiation surface or in its neighborhood. Since the present invention has a very simple configuration, the optical adjustment is easier, and the device becomes compact in size. Furthermore, since the beam is slantly incident with respect to the irradiated body, the return beam can be prevented.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: July 30, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koichiro Tanaka, Hidekazu Miyairi, Aiko Shiga, Akihisa Shimomura, Atsuo Isobe
  • Patent number: 10361222
    Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formulation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba
  • Publication number: 20190221586
    Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
    Type: Application
    Filed: December 4, 2018
    Publication date: July 18, 2019
    Inventors: Wataru UESUGI, Hikaru TAMURA, Atsuo ISOBE
  • Publication number: 20190157309
    Abstract: Provided is a semiconductor device which has low power consumption and can operate at high speed. The semiconductor device includes a memory element including a first transistor including crystalline silicon in a channel formation region, a capacitor for storing data of the memory element, and a second transistor which is a switching element for controlling supply, storage, and release of charge in the capacitor. The second transistor is provided over an insulating film covering the first transistor. The first and second transistors have a source electrode or a drain electrode in common.
    Type: Application
    Filed: January 24, 2019
    Publication date: May 23, 2019
    Inventors: Yoshinori IEDA, Atsuo ISOBE, Yutaka SHIONOIRI, Tomoaki ATSUMI