Patents by Inventor Atsuo KAWAGOE

Atsuo KAWAGOE has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240121903
    Abstract: To improve the peel strength of a wiring pattern formed at a cavity bottom portion while enabling connection between an electronic component inside a cavity and a circuit outside the cavity to be performed at the cavity bottom portion. A method of manufacturing a printed wiring board according to the present disclosure includes performing pattern plating on a substrate made of insulating resin. Forming an electrical conductor layer on a seed layer of a second face, forming a first insulating resin layer on a first face and forming a second insulating resin layer. Drilling in and removing the insulating resin to form a cavity. Removing, by laser machining, a remaining portion of the substrate in the cavity and exposing a surface position of the second insulating resin layer to be equivalent to a surface position of the electrical conductor layer embedded in the second insulating resin layer.
    Type: Application
    Filed: December 18, 2023
    Publication date: April 11, 2024
    Applicant: KYOCERA Corporation
    Inventors: Atsuo KAWAGOE, Naoki ASABA
  • Publication number: 20240040693
    Abstract: A printed wiring board includes a dielectric layer, a first and second conductor layer, and a plurality of via conductors. The dielectric layer has first and second opposing surfaces. The first and second conductor layer lie in the first second surfaces of the dielectric layer, respectively. Each via conductor extends through the dielectric layer and connects the first and second conductor layers to each other. Part of the printed wiring board is surrounded with the via conductors and is an overlap between the first conductor layer and the second conductor layer in a transparent plan view. When viewed in plan, the via conductors each have an aspect ratio greater than 1 and a major axis extending in a first direction and a minor axis extending in a second direction. The via conductors include a via conductor whose major axis extends and connects the via conductors arranged in a line.
    Type: Application
    Filed: December 10, 2021
    Publication date: February 1, 2024
    Applicant: KYOCERA Corporation
    Inventors: Atsuo KAWAGOE, Takashi ISHIOKA, Masanori NAITO, Nobuyuki UEDA
  • Patent number: 11849546
    Abstract: A printed circuit board which improves the peel strength of a wiring pattern formed at a cavity bottom portion while enabling connection between an electronic component inside a cavity and a circuit outside the cavity to be performed at the cavity bottom portion, includes a cavity in a partial region of a multilayer substrate laminated with an insulating resin layer and an electrical conductor layer on a bottom layer of an insulating resin substrate. The cavity opens on a side of the insulating resin substrate, penetrates the insulating resin substrate, and includes a surface of the insulating resin layer as a bottom surface. The electrical conductor layer has a surface, the surface having a height equivalent to a height of the surface of the insulating resin layer and being embedded in the insulating resin layer in a manner to form a portion of the bottom surface.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: December 19, 2023
    Assignee: KYOCERA Corporation
    Inventors: Atsuo Kawagoe, Naoki Asaba
  • Publication number: 20220338357
    Abstract: A printed circuit board which improves the peel strength of a wiring pattern formed at a cavity bottom portion while enabling connection between an electronic component inside a cavity and a circuit outside the cavity to be performed at the cavity bottom portion, includes a cavity in a partial region of a multilayer substrate laminated with an insulating resin layer and an electrical conductor layer on a bottom layer of an insulating resin substrate. The cavity opens on a side of the insulating resin substrate, penetrates the insulating resin substrate, and includes a surface of the insulating resin layer as a bottom surface. The electrical conductor layer has a surface, the surface having a height equivalent to a height of the surface of the insulating resin layer and being embedded in the insulating resin layer in a manner to form a portion of the bottom surface.
    Type: Application
    Filed: September 25, 2019
    Publication date: October 20, 2022
    Applicant: KYOCERA Corporation
    Inventors: Atsuo KAWAGOE, Naoki ASABA