Patents by Inventor Atsuo Oumiya

Atsuo Oumiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device and method of testing short circuits between word lines and bit lines
    Patent number: 6781902
    Abstract: The present invention provides a semiconductor device and a testing method capable of easily detecting a short circuit in a memory circuit with high precision and efficiently detecting a short circuit in a memory circuit. A memory circuit in which memory cells are disposed at intersections of a plurality of word lines and a plurality of bit lines performs, in a test mode, an operation of applying a predetermined potential to neighboring ones of a plurality of word lines or bit lines, an operation of selecting a plurality of word lines and applying a ground potential of the circuit to all of the plurality of bit lines, and an operation of setting all of the plurality of bit lines at a predetermined potential corresponding to the selection level of the word lines and setting all of the plurality of word lines into a non-selection state.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: August 24, 2004
    Assignees: Renesas Technology Corp., Renesas Northern Japan Semiconductor, Inc., Hitachi Device Engineering Co., Ltd.
    Inventors: Atsuo Oumiya, Kouta Tanaka, Naoki Handa, Kenji Kobayashi
  • Semiconductor device and a method of testing thereof
    Publication number: 20040042279
    Abstract: The present invention provides a semiconductor device and a testing method capable of easily detecting a short circuit in a memory circuit with high precision and efficiently detecting a short circuit in a memory circuit. A memory circuit in which memory cells are disposed at intersections of a plurality of word lines and a plurality of bit lines performs, in a test mode, an operation of applying a predetermined potential to neighboring ones of a plurality of word lines or bit lines, an operation of selecting a plurality of word lines and applying a ground potential of the circuit to all of the plurality of bit lines, and an operation of setting all of the plurality of bit lines at a predetermined potential corresponding to the selection level of the word lines and setting all of the plurality of word lines into a non-selection state.
    Type: Application
    Filed: July 9, 2003
    Publication date: March 4, 2004
    Applicants: Hitachi, Ltd., Renesas Northern Japan Semiconductor, Inc., Hitachi Device Engineering Co., Ltd.
    Inventors: Atsuo Oumiya, Kouta Tanaka, Naoki Handa, Kenji Kobayashi