Patents by Inventor Atsuo Yamaguchi
Atsuo Yamaguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9092619Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.Type: GrantFiled: December 2, 2011Date of Patent: July 28, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Hirokazu Tsuruta, Atsuo Yamaguchi, Shigenori Miyauchi
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Patent number: 9052975Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.Type: GrantFiled: August 2, 2012Date of Patent: June 9, 2015Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuhiko Fukushima, Atsuo Yamaguchi
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Patent number: 8848459Abstract: To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization to “0” (a first state) of two states of “0” and “1” (a second state), and which can generate a signal having a potential corresponding to initialized “0”. The semiconductor device 10 includes a plurality of flip-flop circuits 2 that are connected in parallel and which can hold the two states of “0” and “1”; and an AND circuit 3 which generates and outputs a signal having a potential corresponding to “0” when a state held in at least one flip-flop circuit 2 among the flip-flop circuits 2 is “0”. The AND circuit is connected to the flip-flop circuits 2.Type: GrantFiled: March 13, 2012Date of Patent: September 30, 2014Assignee: Renesas Electronics CorporationInventors: Kazuhiko Fukushima, Atsuo Yamaguchi
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Patent number: 8619991Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.Type: GrantFiled: June 29, 2011Date of Patent: December 31, 2013Assignee: Renesas Electronics CorporationInventors: Shigenori Miyauchi, Atsuo Yamaguchi
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Patent number: 8559634Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.Type: GrantFiled: August 23, 2012Date of Patent: October 15, 2013Assignee: Renesas Electronics CorporationInventors: Shigenori Miyauchi, Atsuo Yamaguchi
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Publication number: 20120314858Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.Type: ApplicationFiled: August 23, 2012Publication date: December 13, 2012Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Shigenori Miyauchi, Atsuo Yamaguchi
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Publication number: 20120303690Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.Type: ApplicationFiled: August 2, 2012Publication date: November 29, 2012Inventors: Kazuhiko FUKUSHIMA, Atsuo Yamaguchi
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Publication number: 20120250432Abstract: To provide a semiconductor device which can perform initialization to a first state of two states of the first state and a second state, and which can generate a signal having a potential corresponding to the initialized first state. The present invention is the semiconductor device which can perform initialization to “0” (a first state) of two states of “0” and “1” (a second state), and which can generate a signal having a potential corresponding to initialized “0”. The semiconductor device 10 includes a plurality of flip-flop circuits 2 that are connected in parallel and which can hold the two states of “0” and “1”; and an AND circuit 3 which generates and outputs a signal having a potential corresponding to “0” when a state held in at least one flip-flop circuit 2 among the flip-flop circuits 2 is “0”. The AND circuit is connected to the flip-flop circuits 2.Type: ApplicationFiled: March 13, 2012Publication date: October 4, 2012Inventors: Kazuhiko FUKUSHIMA, Atsuo Yamaguchi
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Patent number: 8260835Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.Type: GrantFiled: August 18, 2008Date of Patent: September 4, 2012Assignees: Renesas Electronics Corporation, Renesas LSI Design CorporationInventors: Kazuhiko Fukushima, Atsuo Yamaguchi
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Publication number: 20120079286Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.Type: ApplicationFiled: December 2, 2011Publication date: March 29, 2012Applicant: Renesas Electronics CorporationInventors: Hirokazu TSURUTA, Atsuo Yamaguchi, Shigenori Miyauchi
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Patent number: 8140858Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.Type: GrantFiled: March 10, 2009Date of Patent: March 20, 2012Assignee: Renesas Electronics CorporationInventors: Hirokazu Tsuruta, Atsuo Yamaguchi, Shigenori Miyauchi
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Publication number: 20110255694Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.Type: ApplicationFiled: June 29, 2011Publication date: October 20, 2011Applicant: Renesas Electronics Corp.Inventors: Shigenori Miyauchi, Atsuo Yamaguchi
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Publication number: 20090259856Abstract: A data processing apparatus is provided, which detects falsification of software to data and rewriting of the data. The data processing apparatus according to an embodiment of the present invention comprises a security unit which has an encryption circuit for decrypting an encrypted signal including secrecy data. The security unit includes a compression circuit which compresses an access signal used in accessing the security unit and outputs the compression result, and a comparison circuit which compares the compression result outputted from the compression circuit with a previously-calculated expectation value of the compression result of the access signal.Type: ApplicationFiled: March 10, 2009Publication date: October 15, 2009Inventors: Hirokazu Tsuruta, Atsuo Yamaguchi, Shigenori Miyauchi
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Patent number: 7471789Abstract: An addition and subtraction circuit performs addition and subtraction using a carry-in signal from another operation circuit, and outputs a carry-out signal generated through addition and subtraction to another operation circuit. A right-shift circuit performs right-shift using a shift-in signal from another operation circuit, and outputs a shift-out signal generated through right-shift to another operation circuit. Therefore, even if a data length of operation data is extended, a propagation path for a carry can be shortened, and an operation clock frequency of an encryption circuit can be increased.Type: GrantFiled: August 26, 2003Date of Patent: December 30, 2008Assignee: Renesas Technology Corp.Inventors: Shigenori Miyauchi, Atsuo Yamaguchi
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Publication number: 20080313249Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.Type: ApplicationFiled: August 18, 2008Publication date: December 18, 2008Applicants: RENESAS TECHNOLOGY CORP., RENESAS LSI DESIGN CORPORATIONInventors: Kazuhiko Fukushima, Atsuo Yamaguchi
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Patent number: 7424500Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.Type: GrantFiled: June 24, 2004Date of Patent: September 9, 2008Assignees: Renesas Technology Corp., Renesas LSI Design CorporationInventors: Kazuhiko Fukushima, Atsuo Yamaguchi
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Patent number: 7171437Abstract: A power-residue calculating unit includes a K register connected to a first internal bus for once storing an intermediate calculation result to be discarded when a power-residue calculation is executed in accordance with a binary method. Therefore even when data to be discarded appears during the calculation, a write into K register is performed, so that current in a write operation flows thereby improving immunity against Power Analysis.Type: GrantFiled: July 9, 2003Date of Patent: January 30, 2007Assignee: Renesas Technology Corp.Inventor: Atsuo Yamaguchi
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Publication number: 20070014396Abstract: An encoding/decoding operation portion includes an encoding/decoding operation circuit and an avoiding path for detouring the encoding/decoding operation circuit and can select between encoding or decoding input data in the encoding/decoding operation circuit and detouring the encoding/decoding operation circuit to output the input data without change. Only one wire has to be provided from a selector to a key storage portion and an initialization-vector storage portion. With this construction, it is possible to realize an encoding/decoding circuit which can suppress an increase in the number of wires used to transmit a content of key data to the key storage portion and the initialization-vector storage portion and does not cause complication of circuit layout.Type: ApplicationFiled: July 11, 2006Publication date: January 18, 2007Applicant: Renesas Technology Corp.Inventors: Shigenori Miyauchi, Atsuo Yamaguchi
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Publication number: 20050055531Abstract: A free page extracting unit extracts a free page of a non-volatile memory. A directory page writing unit writes, to the free page extracted by the free page extracting unit, a directory that includes a logical page/physical page translation table of a page to which updated data are to be written. Further, a data page writing unit writes updated data to the free page extracted by the free page extracting unit. Therefore, even when data updating operation is interrupted, loss of the original data can be prevented, and the data before updating can be recovered.Type: ApplicationFiled: February 25, 2004Publication date: March 10, 2005Applicants: Renesas Technology Corp., Renesas LSI Design CorporationInventors: Kazuo Asami, Atsuo Yamaguchi
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Publication number: 20050052280Abstract: When a CPU proceeds to an interruption process, a value permitting an access to a security-related area is set in a flag register, and when the CPU returns from the interruption process, a value prohibiting an access to the security-related area is set in the flag register. A resource selecting signal generating circuit generates access signals for accessing to various areas in a non-volatile memory and an RAM, in accordance with the flag stored in the flag register. Therefore, when the security-related area is held as an interruption processing area, it becomes possible to prevent an access to the security-related area from a security-non-related program area, and hence, it becomes possible to prevent leakage of security-related information.Type: ApplicationFiled: September 2, 2004Publication date: March 10, 2005Inventors: Kazuhiko Fukushima, Atsuo Yamaguchi