Patents by Inventor Atsushi Amo
Atsushi Amo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230299197Abstract: A semiconductor device is provided with an SOI substrate which includes a semiconductor substrate, a ferroelectric layer and a semiconductor layer, and has a first region in which a first MISFET is formed. The first MISFET includes: the semiconductor substrate in the first region; the ferroelectric layer in the first region; the semiconductor layer in the first region; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first source region located on one side of the first gate electrode and formed in the semiconductor layer in the first region; and a first drain region located on the other side of the first gate electrode and formed in the semiconductor layer in the first region.Type: ApplicationFiled: March 17, 2022Publication date: September 21, 2023Inventors: Eiji TSUKUDA, Tohru KAWAI, Atsushi AMO
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Publication number: 20230093724Abstract: A method of manufacturing a semiconductor device capable of detecting occurrence of a Hi-K disappearance is provided. The method of manufacturing a semiconductor device includes a step of manufacturing a test pattern including a reference resistance, a gate leakage resistance through which a gate leakage current flows and connected in series with the reference resistance, and a step of measuring a change in voltage at a connection node between the reference resistance and the gate leakage resistance caused by the flow of the gate leakage current.Type: ApplicationFiled: July 28, 2022Publication date: March 23, 2023Inventors: Atsushi AMO, Hiraku CHAKIHARA, Hiroshi YANAGITA, Akio ONO
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Patent number: 11563111Abstract: A trench is formed by removing a portion of each of the charge accumulation film and the insulating film located between the control gate electrode and the memory gate electrode. The insulating film is formed in the trench so that the upper surface of each of the insulating film and the charge accumulation film is covered with the insulating film. When exposing the upper surface of the control gate electrode and the memory gate electrode, the upper surface of each of the insulating film and the charge accumulation film is not exposed.Type: GrantFiled: July 14, 2020Date of Patent: January 24, 2023Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Publication number: 20210036132Abstract: A trench is formed by removing a portion of each of the charge accumulation film and the insulating film located between the control gate electrode and the memory gate electrode. The insulating film is formed in the trench so that the upper surface of each of the insulating film and the charge accumulation film is covered with the insulating film. When exposing the upper surface of the control gate electrode and the memory gate electrode, the upper surface of each of the insulating film and the charge accumulation film is not exposed.Type: ApplicationFiled: July 14, 2020Publication date: February 4, 2021Inventor: Atsushi AMO
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Patent number: 10847628Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a first conductive film that is located over the first surface and is formed to circle in plan view; a second conductive film that is located over the first surface and surrounds the outer periphery of the first conductive film in plan view; a first insulating spacer located between the first conductive film and the second conductive film; a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate; and a second gate insulating film located between the first surface and the second conductive film.Type: GrantFiled: February 22, 2019Date of Patent: November 24, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Publication number: 20190280096Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a first surface; a first conductive film that is located over the first surface and is formed to circle in plan view; a second conductive film that is located over the first surface and surrounds the outer periphery of the first conductive film in plan view; a first insulating spacer located between the first conductive film and the second conductive film; a first gate insulating film that is located between the first surface and the first conductive film and the accumulated amount of charges of which changes due to a change in the voltage between the first conductive film and the semiconductor substrate; and a second gate insulating film located between the first surface and the second conductive film.Type: ApplicationFiled: February 22, 2019Publication date: September 12, 2019Inventor: Atsushi AMO
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Patent number: 10243085Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.Type: GrantFiled: July 24, 2017Date of Patent: March 26, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Patent number: 10211348Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.Type: GrantFiled: March 7, 2018Date of Patent: February 19, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Patent number: 10205006Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a main surface, the main surface including a first area and a second area, which is different from the first area in a plan view, forming a first trench in the main surface of the semiconductor substrate in the first area, after the forming the first trench, forming a first insulating film on a side wall surface and a bottom face of the first trench, and after the forming the first insulating film, forming a first conductor film over the semiconductor substrate in the first area and a second area to embed a portion of the first conductor film into the first trench through the first insulating film.Type: GrantFiled: April 12, 2018Date of Patent: February 12, 2019Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Publication number: 20180233587Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor substrate including a main surface, the main surface including a first area and a second area, which is different from the first area in a plan view, forming a first trench in the main surface of the semiconductor substrate in the first area, after the forming the first trench, forming a first insulating film on a side wall surface and a bottom face of the first trench, and after the forming the first insulating film, forming a first conductor film over the semiconductor substrate in the first area and a second area to embed a portion of the first conductor film into the first trench through the first insulating film.Type: ApplicationFiled: April 12, 2018Publication date: August 16, 2018Inventor: Atsushi Amo
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Publication number: 20180198001Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.Type: ApplicationFiled: March 7, 2018Publication date: July 12, 2018Inventor: Atsushi AMO
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Patent number: 9954120Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.Type: GrantFiled: July 27, 2017Date of Patent: April 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Patent number: 9947776Abstract: To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an upper electrode is embedded in a trench formed in a main surface of a semiconductor substrate are mixed together. After an insulating film is formed over a main surface of a semiconductor substrate so as to cover a trench formed in the main surface of the semiconductor substrate, the insulating film is processed to form an upper electrode of a capacitive element, a gate insulating film which insulates the semiconductor substrate to be a lower electrode, and a gate insulting film of a high breakdown voltage transistor.Type: GrantFiled: January 26, 2017Date of Patent: April 17, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Publication number: 20170323980Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.Type: ApplicationFiled: July 24, 2017Publication date: November 9, 2017Inventor: Atsushi AMO
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Publication number: 20170323983Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.Type: ApplicationFiled: July 27, 2017Publication date: November 9, 2017Inventor: Atsushi AMO
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Publication number: 20170278954Abstract: To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an upper electrode is embedded in a trench formed in a main surface of a semiconductor substrate are mixed together. After an insulating film is formed over a main surface of a semiconductor substrate so as to cover a trench formed in the main surface of the semiconductor substrate, the insulating film is processed to form an upper electrode of a capacitive element, a gate insulating film which insulates the semiconductor substrate to be a lower electrode, and a gate insulting film of a high breakdown voltage transistor.Type: ApplicationFiled: January 26, 2017Publication date: September 28, 2017Inventor: Atsushi Amo
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Patent number: 9755086Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.Type: GrantFiled: January 30, 2016Date of Patent: September 5, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Patent number: 9748407Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.Type: GrantFiled: February 14, 2016Date of Patent: August 29, 2017Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Publication number: 20160293776Abstract: An object is to provide a reliability-improved semiconductor device having a MONOS memory that rewrites data by injecting carriers into a charge storage portion. When a memory gate electrode having a small gate length is formed in order to overlap a carrier injection position in write operation with that in erase operation, each into an ONO film including a charge storage portion, the ONO film is formed in a recess of a main surface of a semiconductor substrate for securing a large channel length. In a step of manufacturing this structure, control gate electrodes are formed by stepwise processing of a polysilicon film by first and second etching and then, the recess is formed in the main surface of the semiconductor substrate on one side of the control gate electrode by second etching.Type: ApplicationFiled: February 14, 2016Publication date: October 6, 2016Inventor: Atsushi AMO
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Publication number: 20160268445Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.Type: ApplicationFiled: January 30, 2016Publication date: September 15, 2016Inventor: Atsushi AMO