Patents by Inventor Atsushi Awano

Atsushi Awano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8110752
    Abstract: A method for manufacturing a wiring substrate includes forming a conductor circuit on an insulating layer, the conductor circuit including a pad, a circuit pattern connected to the pad, and a lead pattern connected to the pad. A solder resist layer is formed on the circuit pattern and on the insulating layer, and a plating resist layer is formed on the lead pattern and on the insulating layer and forming a metal film on a first portion of the conductor circuit not covered by the solder resist layer and not covered by the plating resist layer. The plating resist layer is removed to expose a second portion of the conductor circuit adjacent to the first portion of the conductor circuit and not covered with the metal film, and an etching resist layer is formed on the metal film and on the second portion of the conductor circuit. A third portion of the conductor circuit not covered by the etching resist layer is removed by etching, and the etching resist is removed.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: February 7, 2012
    Assignee: Ibiden Co., Ltd.
    Inventors: Fusaji Nagaya, Nobuhisa Kuroda, Atsushi Awano
  • Publication number: 20090260853
    Abstract: A method for manufacturing a wiring substrate includes forming a conductor circuit on an insulating layer, the conductor circuit including a pad, a circuit pattern connected to the pad, and a lead pattern connected to the pad. A solder resist layer is formed on the circuit pattern and on the insulating layer, and a plating resist layer is formed on the lead pattern and on the insulating layer and forming a metal film on a first portion of the conductor circuit not covered by the solder resist layer and not covered by the plating resist layer. The plating resist layer is removed to expose a second portion of the conductor circuit adjacent to the first portion of the conductor circuit and not covered with the metal film, and an etching resist layer is formed on the metal film and on the second portion of the conductor circuit. A third portion of the conductor circuit not covered by the etching resist layer is removed by etching, and the etching resist is removed.
    Type: Application
    Filed: March 30, 2009
    Publication date: October 22, 2009
    Applicant: IBIDEN CO., LTD.
    Inventors: Fusaji Nagaya, Nobuhisa Kuroda, Atsushi Awano