Abstract: Provided is a kneaded material including an ultraviolet absorbing agent that contains at least one compound selected from a compound represented by Formula (1) or a compound represented by Formula (2), and a polymer compound.

Abstract: Provided are a photopolymerizable composition including at least one compound selected from a compound represented by Formula (1) or a compound represented by Formula (2), a polymerizable compound, and a photopolymerization initiator, and a cured substance and an optical member which are formed of the photopolymerizable composition.

Abstract: Provided are an ultraviolet absorbing agent including a compound represented by Formula (1), in which the ultraviolet absorbing agent has a maximum absorption wavelength in a wavelength range of 350 to 390 nm in an ethyl acetate solution, and a value obtained by dividing an absorbance at a wavelength of 430 nm by an absorbance at the maximum absorption wavelength is 0.01 or less, a resin composition, a cured substance, and an optical member which include the ultraviolet absorbing agent, a method of producing an ultraviolet absorbing agent, and a compound. In Formula (1), X1 and X2 each independently represent a cyano group or the like, R1 and R2 each independently represent an alkyl group or the like, and R3 and R4 each independently represent a hydrogen atom, a halogen atom, an alkyl group, an aryl group, an alkoxy group, or an aryloxy group.

Abstract: Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.

Abstract: Semiconductor layout generation includes: calculating, for a design rule constraint, a slack value for a subset of elements of a proposed semiconductor layout; generating a plurality of alternative layouts, where each of the alternative layouts includes a variation of interdependent characteristics of the subset of elements and a slack value for the subset of elements of each of the alternative layouts is less than the calculated slack value of subset of elements of the proposed layout; and calculating, by the layout design module for each of the alternative layouts, a risk value indicating the alternative layout's risk of fabrication failure.

Abstract: A low-molecular-weight polysulfated hyaluronic acid derivative useful for treatment of an allergic disease. An agent for treatment of an allergic disease selected from pollinosis, allergic rhinitis, allergic conjunctivitis, atopic dermatitis, and asthma, represented by the following general formula (IA) or (IB); wherein n represents a number of 0 to 15; R's each independently represent a hydrogen atom or an SO3H group etc.

Abstract: A low-molecular-weight polysulfated hyaluronic acid derivative useful for prevention and/or treatment of an allergic disease. An agent for prevention and/or treatment of an allergic disease selected from pollinosis, allergic rhinitis, allergic conjunctivitis, atopic dermatitis, and asthma, represented by the following general formula (IA) or (IB); wherein n represents a number of 0 to 15; R?s each independently represent a hydrogen atom or an SO3H group etc.

Abstract: A semiconductor device including a SRAM cell may include a data holding unit including a driver transistor and a load transistor, and receiving and holding data; and a data transferring unit including a transfer gate transistor whose source and drain are connected between the data holding unit and one of a pair of bit lines, and whose gate is connected to a word line, the data transferring unit either transferring the data transferred from the one of the pair of bit lines to the data holding unit or receiving the data held in the data holding unit and transferring the data to the one of the pair of bit lines, wherein at least one of the driver transistor and the load transistor has higher capacitance between the gate and the source and between the gate and the drain than the transfer gate transistor.

Abstract: A semiconductor device including a SRAM cell may include a data holding unit including a driver transistor and a load transistor, and receiving and holding data; and a data transferring unit including a transfer gate transistor whose source and drain are connected between the data holding unit and one of a pair of bit lines, and whose gate is connected to a word line, the data transferring unit either transferring the data transferred from the one of the pair of bit lines to the data holding unit or receiving the data held in the data holding unit and transferring the data to the one of the pair of bit lines, wherein at least one of the driver transistor and the load transistor has higher capacitance between the gate and the source and between the gate and the drain than the transfer gate transistor.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.

Abstract: A partially-depleted silicon-on-insulator (SOI) field-effect transistor (FET) with a reduced off-current is described, as well as methods for manufacturing. This may be accomplished by providing an SOI FET having a lower body potential than in previous SOI FETs. To lower the body potential, carrier traps may be formed mainly in the neutral source and drain regions of the SOI FET by extra over-etching of the gate spacers and the underlying silicon layer.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.

Abstract: In the SOI region of a semiconductor substrate, a BOX layer is formed underneath with backgate electrodes to control the threshold voltages of MOS transistors formed in the SOI region.

Abstract: The present invention provides a semiconductor device, comprising a gate electrode of a stacked structure consisting of a polysilicon layer and a metal layer, a cap insulating film formed on the gate electrode, and a gate side wall film formed on the side wall of the gate electrode. The cap insulating film consists of an insulating film containing a silicon oxide-based layer and a silicon nitride layer and serves to protect the upper surface of the gate electrode. Further, the gate side wall film consists of an insulating film containing a silicon nitride film and a silicon oxide film and serves to protect the side surface of the gate electrode.

Abstract: A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.

Abstract: The present invention provides a semiconductor device, comprising a gate electrode of a stacked structure consisting of a polysilicon layer and a metal layer, a cap insulating film formed on the gate electrode, and a gate side wall film formed on the side wall of the gate electrode. The cap insulating film consists of an insulating film containing a silicon oxide-based layer and a silicon nitride layer and serves to protect the upper surface of the gate electrode. Further, the gate side wall film consists of an insulating film containing a silicon nitride film and a silicon oxide film and serves to protect the side surface of the gate electrode.

Abstract: A DNA array for measuring sensitivity to an antimetabolite-type anticancer agent or a combined use of such an anticancer agent and another anticancer agent, characterized by including at least 13 types of target gene fragments, involving at least two types of genes selected from each of the following groups: nucleic acid metabolism-associated enzyme genes, gene repair-associated enzyme genes, drug resistance-associated factor genes and housekeeping genes, wherein these gene fragments have been selected by the following steps 1) and 2) and immobilized on a substrate; 1) a step of selecting fragments having high specificity for target genes by searching the homology with the use of databases; and 2) a step of performing Northern hybridization against RNA obtained from tumor cells with the use of the fragments selected in the step 1) as probes to thereby confirm the specificity for the target genes.

Abstract: A convex polycrystalline silicon film is formed on a handle wafer. A semiconductor layer is formed on the polycrystalline silicon film. The semiconductor is thinner on its areas in which the convex polycrystalline silicon film is formed and is thicker on its areas in which the convex polycrystalline silicon film is not formed. An opening is formed in each of those areas of an insulating film which are located under respective thick-film semiconductor areas of the semiconductor layer. The polycrystalline silicon film is formed in the openings to connect electrically the thick-film semiconductor areas and the handle wafer together.

Abstract: In the SOI region of a semiconductor substrate, a BOX layer is formed underneath with backgate electrodes to control the threshold voltages of MOS transistors formed in the SOI region.

Abstract: A semiconductor device includes a gate insulating film formed on a semiconductor substrate between first diffusion layers, a gate electrode including a first gate portion formed on the gate insulating film and a second gate portion formed on the first gate portion, a first width in a channel direction of the first gate portion being substantially equal to a width in that of the gate insulating film, and a second width in the channel direction of the second gate portion being larger than the first width, a gate side wall insulating film including a first side wall portion formed on a side surface of the first gate portion and the gate insulating film and a second side wall portion formed on a side surface of the second gate portion, and a second diffusion layer formed apart from the first diffusion layers below the gate insulating film.