Patents by Inventor Atsushi Ban

Atsushi Ban has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6462792
    Abstract: In a liquid crystal display device, auxiliary lines are formed under pixel electrodes so as to be parallel to signal or scanning lines. The auxiliary lines are connected to the signal or scanning lines at one point for each pixel. This permits a voltage to be applied to a signal or scanning line if a disconnection defect occurs in the signal or scanning line. The auxiliary line is connected to the signal or scanning line at opposite sides of the defect to form a circuit around the defect. Moreover, if a leakage defect occurs at a crossing point between the scanning line and the signal line, the signal or scanning line may be cut off at both sides of the scanning or signal line, and the auxiliary line forms a circuit that avoids the line leak. Thus, a voltage may be applied to the signal or scanning line by the auxiliary line.
    Type: Grant
    Filed: November 24, 2000
    Date of Patent: October 8, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ban, Takayuki Shimada, Mikio Katayama
  • Patent number: 6452654
    Abstract: A liquid crystal display device according to the present invention includes a first substrate, a second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. The first substrate includes: a plurality of gate lines; a plurality of source lines arranged to cross with the plurality of gate lines; a plurality of switching elements disposed in the vicinity of crossings of the plurality of gate lines and the plurality of source lines; and a plurality of pixel electrodes connected to the plurality of switching elements. The second substrate includes a counter electrode. A plurality of pixel regions are defined by the plurality of pixel electrodes, the counter electrode, and the liquid crystal layer interposed between the plurality of pixel electrodes and the counter electrode, and each of the plurality of pixel regions includes a reflection region and a transmission region.
    Type: Grant
    Filed: December 20, 2000
    Date of Patent: September 17, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masumi Kubo, Yozo Narutaki, Atsushi Ban, Takayuki Shimada, Yoji Yoshimura, Mikio Katayama, Yutaka Ishii, Hirohiko Nishiki
  • Patent number: 6417901
    Abstract: The invention provides a liquid crystal display device having a structure in which light reflection on lines can be suppressed and reduction in contrast of the liquid crystal display device can be prevented without providing a shielding film on a color filter of an opposite substrate portion. In the liquid crystal display device according to the invention, a shielding film is not provided in a color filter provided on a substrate on the opposite substrate portion side. A signal line is formed of a transparent conductive material such as ITO, amorphous ITO or the like. Consequently, light incident from the surface of the liquid crystal display device passes through the back face of the liquid crystal display device without causing surface reflection even if the light hits upon the signal line in an interval between pixel electrodes. Consequently, it is possible to prevent reduction in contrast caused by the light reflected on the signal line.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: July 9, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshihiro Okada, Atsushi Ban, Atsuhito Murai, Takashi Sato
  • Publication number: 20020079501
    Abstract: An active matrix substrate includes base substrate, gate lines, data lines, thin-film transistors and pixel electrodes. The gate lines are formed on the base substrate. The data lines are formed over the gate lines. Each of the data lines crosses all of the gate lines with an insulating film interposed therebetween. The thin-film transistors are formed over the base substrate. Each of the thin-film transistors is associated with one of the gate lines and operates responsive to a signal on the associated gate line. Each of the pixel electrodes is associated with one of the data lines and one of the thin-film transistors and is electrically connectable to the associated data line by way of the associated thin-film transistor. Each of the pixel electrodes and the associated thin-film transistor are connected together by way of a conductive member.
    Type: Application
    Filed: August 24, 2001
    Publication date: June 27, 2002
    Inventors: Yoshihiro Okada, Yuichi Saito, Shinya Yamakawa, Atsushi Ban, Masaya Okamoto, Hiroyuki Ohgami
  • Publication number: 20020008685
    Abstract: Pseudo-impulse display for reducing after-images during display of moving images in an active matrix type display apparatus. Liquid crystal capacitors are formed at intersections of signal lines and scanning lines to display images. Auxiliary capacitors are provided for keeping a potential difference across the liquid crystal capacitors during display. One of the two electrodes of the auxiliary capacitors is connected to a switching element together with a pixel electrode. After the liquid crystal capacitor and the auxiliary capacitor have been charged with a video signal on the signal lines while the switching element is selectively put into the conducting state with the scanning lines, and after a predetermined time has passed, an auxiliary capacitor driver applies a signal to the other electrode of the auxiliary capacitor, such that the display luminance due to the liquid crystal capacitor is reduced.
    Type: Application
    Filed: March 15, 2001
    Publication date: January 24, 2002
    Inventors: Atsushi Ban, Yoshihiro Okada, Wataru Nakamura
  • Publication number: 20020003588
    Abstract: In an active matrix type liquid crystal display apparatus, each of pixel electrodes has overhanging portions at its opposite side edges. These overhanging portions of the pixel electrode cover two signal lines placed on opposite sides of the pixel electrode, respectively.
    Type: Application
    Filed: March 29, 2001
    Publication date: January 10, 2002
    Inventors: Yoshihiro Okada, Atsushi Ban
  • Publication number: 20010055082
    Abstract: A liquid crystal display device includes a first substrate; a second substrate; a liquid crystal layer interposed between the first substrate and the second substrate; a first polarizer provided on a surface of the first substrate which is on the opposite side to the liquid crystal layer; a second polarizer provided on a surface of the second substrate which is on the opposite side to the liquid crystal layer; a first phase compensation element provided between the first polarizer and the liquid crystal layer; and a second phase compensation element provided between the second polarizer and the liquid crystal layer. A plurality of pixel areas are provided for display. The first substrate includes at least one transmissive electrode, and the second substrate includes a reflective electrode region and a transmissive electrode region in correspondence with each of the plurality of pixel areas.
    Type: Application
    Filed: August 13, 2001
    Publication date: December 27, 2001
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Masumi Kubo, Yozo Narutaki, Shogo Fujioka, Yuko Maruyama, Takayuki Shimada, Youji Yoshimura, Mikio Katayama, Yutaka Ishii, Shinya Yamakawa, Atsushi Ban
  • Patent number: 6330047
    Abstract: A liquid crystal display device includes a first substrate, a second substrate, and a liquid crystal layer interposed between the first and second substrates, a plurality of pixel regions being defined by respective pairs of electrodes for applying a voltage to the liquid crystal layer, wherein each of the plurality of pixel regions includes a reflection region and a transmission region, and the first substrate includes, a transmission electrode through which light from a light source passes within the transmission region, and a reflection electrode by which ambient light is reflected within the reflection region, wherein the transmission electrode and the reflection electrode are electrically connected to each other in an interface area between the transmission region and the reflection region.
    Type: Grant
    Filed: March 10, 2000
    Date of Patent: December 11, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masumi Kubo, Yozo Narutaki, Atsushi Ban, Takayuki Shimada, Yoji Yoshimura, Mikio Katayama, Yutaka Ishii, Hirohiko Nishiki, Akihiro Yamamoto, Yoshinori Shimada
  • Patent number: 6295109
    Abstract: A liquid crystal display device includes a first substrate; a second substrate; a liquid crystal layer interposed between the first substrate and the second substrate; a first polarizer provided on a surface of the first substrate which is on the opposite side to the liquid crystal layer; a second polarizer provided on a surface of the second substrate which is on the opposite side to the liquid crystal layer; a first phase compensation element provided between the first polarizer and the liquid crystal layer; and a second phase compensation element provided between the second polarizer and the liquid crystal layer. A plurality of pixel areas are provided for display. The first substrate includes at least one transmissive electrode, and the second substrate includes a reflective electrode region and a transmissive electrode region in correspondence with each of the plurality of pixel areas.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: September 25, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masumi Kubo, Yozo Narutaki, Shogo Fujioka, Yuko Maruyama, Takayuki Shimada, Youji Yoshimura, Mikio Katayama, Yutaka Ishii, Shinya Yamakawa, Atsushi Ban
  • Publication number: 20010020991
    Abstract: A liquid crystal display device according to the present invention includes a first substrate, a second substrate, and a liquid, crystal layer interposed between the first substrate and the second substrate. The first substrate includes: a plurality of gate lines; a plurality of source lines arranged to cross with the plurality of gate lines; a plurality of switching elements disposed in the vicinity of crossings of the plurality of gate lines and the plurality of source lines; and a plurality of pixel electrodes connected to the plurality of switching elements. The second substrate includes a counter electrode. A plurality of pixel regions are defined by the plurality of pixel electrodes, the counter electrode, and the liquid crystal layer interposed between the plurality of pixel electrodes and the counter electrode, and each of the plurality of pixel regions includes a reflection region and a transmission region.
    Type: Application
    Filed: December 20, 2000
    Publication date: September 13, 2001
    Inventors: Masumi Kubo, Yozo Narutaki, Atsushi Ban, Takayuki Shimada, Yoji Yoshimura, Mikio Katayama, Yutaka Ishii, Hirohiko Nishiki
  • Patent number: 6284576
    Abstract: A thin-film transistor of the reversed stagger type is provided with a gate electrode, first and second gate insulating films, a semiconductor layer, separated contact layers, and source electrodes and drain electrodes, all of which are stacked on a substrate. Upon manufacturing the thin-film transistor of this type, a gap section is pattered in a single contact-material layer. In this case, the contact-material layer is patterned by a dry etching with etching gases including HCl+SF6 or CF4+O2+HCl by the use of the source electrode and drain electrode as direct masks. Upon patterning a gap section in the contact-material layer between the source electrode and the drain electrode, no dedicated resist pattern is required; therefore, it is possible to reduce the number of the processes as compared with conventional manufacturing methods. Consequently, it becomes possible to reduce the production cost of thin-film transistors and also to improve the yield of desired products.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: September 4, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ban, Hisataka Suzuki, Masaya Okamoto
  • Patent number: 6195140
    Abstract: A liquid crystal display device according to the present invention includes a first substrate, a second substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. The first substrate includes: a plurality of gate lines; a plurality of source lines arranged to cross with the plurality of gate lines; a plurality of switching elements disposed in the vicinity of crossings of the plurality of gate lines and the plurality of source lines; and a plurality of pixel electrodes connected to the plurality of switching elements. The second substrate includes a counter electrode. A plurality of pixel regions are defined by the plurality of pixel electrodes, the counter electrode, and the liquid crystal layer interposed between the plurality of pixel electrodes and the counter electrode, and each of the plurality of pixel regions includes a reflection region and a transmission region.
    Type: Grant
    Filed: July 27, 1998
    Date of Patent: February 27, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masumi Kubo, Yozo Narutaki, Atsushi Ban, Takayuki Shimada, Yoji Yoshimura, Mikio Katayama, Yutaka Ishii, Hirohiko Nishiki
  • Patent number: 6184960
    Abstract: A method for producing a substrate of a reflection type liquid crystal display device is provided. The method includes the steps of: forming the input portion for inputting a signal from outside and the connecting electrode on the substrate on which the reflective electrode is formed; forming a protective film on the connecting electrode; forming an interlayer insulator under the condition that the protective film on the connecting electrode is exposed; patterning the interlayer insulator; forming a reflective electrode film on the interlayer insulator; patterning the reflective electrode film to form the reflective electrode; and removing the protective film on the connecting electrode to expose the connecting electrode.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: February 6, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Sawayama, Koji Taniguchi, Shinya Yamakawa, Atsushi Ban, Yoshihiro Okada, Atsuhito Murai, Takayuki Shimada
  • Patent number: 6175393
    Abstract: Auxiliary lines are formed under pixel electrodes so as to be parallel to signal lines. The auxiliary lines are connected to the signal lines at one point for each pixel. This permits a voltage to be kept applying to a signal line even if a disconnection defect occurs in the signal line by making a circuit around a disconnected portion by the auxiliary line. Moreover, if a leakage defect occurs at a crossing point between the scanning line and the signal line, the signal line would be cut off on both sides of the scanning line. This also permits a voltage to be kept applying to the signal line by the auxiliary line. By setting the auxiliary lines narrower than the signal line, a reduction in aperture ratio can be suppressed, and by adopting the auxiliary lines made of a transparent electrically conductive material such as ITO, etc., it is possible to prevent the reduction in aperture ratio due to the auxiliary lines.
    Type: Grant
    Filed: August 20, 1996
    Date of Patent: January 16, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ban, Takayuki Shimada, Mikio Katayama
  • Patent number: 6133157
    Abstract: In a method for selectively etching a second silicon layer of a multilayer structure which includes a first silicon layer and the second silicon layer formed on the first silicon layer and doped with impurities according to the present invention, the second silicon layer is selectively etched by using an etching gas including freon-14 gas and a gas selected from a group composed of hydrogen chloride gas and chloride gas.
    Type: Grant
    Filed: July 21, 1998
    Date of Patent: October 17, 2000
    Assignee: Sharp Kabushike Kaisha
    Inventors: Takehisa Sakurai, Hitoshi Ujimasa, Katsuhiro Kawai, Atsushi Ban, Masaru Kajitani, Mikio Katayama
  • Patent number: 6111620
    Abstract: An active matrix substrate provided with a dielectric substrate, on which a gate wire multi-short-circuit group composed of gate wire multi-short-circuit wires and a data wire multi-short-circuit group composed of gate wire multi-short-circuit wires are formed at either ends of the gate wires and data wires, respectively. The gate wires and gate wire multi-short-circuit wires are connected in such a manner that adjacent gate wires are short-circuited with different gate wire multi-short-circuit wires. It has become possible with the present active matrix substrate to conduct electrical inspections such that can detect leakage defects among the gate wires and those among the data wires, correct the revealed defects, and confirm the corrections easier at a low cost. Moreover, the present active matrix substrate can prevent static electricity in a sufficient manner.
    Type: Grant
    Filed: August 28, 1996
    Date of Patent: August 29, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hirohiko Nishiki, Takayuki Shimada, Atsushi Ban, Naofumi Kondo
  • Patent number: 6072559
    Abstract: The active matrix display device of this invention includes: a substrate and a scanning line running in a first direction formed in a first layer located above the substrate. The display device also includes a signal line running in a second direction formed in a second layer located above the substrate; a switching element connected with the scanning line and the signal line; an insulating film formed above the scanning line, the signal line, and the switching element; and a pixel electrode formed above the insulating film so as to connect with the switching element, wherein the active matrix display device further comprises an extension line connected with an electrode of the switching element, the extension line being formed in the second layer so as not to intersect the signal line.
    Type: Grant
    Filed: March 6, 1997
    Date of Patent: June 6, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yuzuru Kanemori, Atsushi Ban, Mikio Katayama
  • Patent number: 6034747
    Abstract: An active matrix substrate includes a gate line, a source line, and a thin film transistor provided in the vicinity of an intersection between the gate line and the source line. The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the source line, and a drain electrode connected to a pixel electrode. An interlayer insulating film is provided over the thin film transistor, the gate line, and the source line. The pixel electrode is provided on the interlayer insulating film, and is connected to the drain electrode via a contact hole formed in the interlayer insulating film. A conductive layer extends over a channel region of the thin film transistor via the interlayer insulating film.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: March 7, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Shinya Tanaka, Atsushi Ban, Takayuki Shimada, Mikio Katayama
  • Patent number: 5981972
    Abstract: An active matrix substrate of a Pixel on Passivation structure includes TFTs and pixel electrodes on an interlayer insulating film over bus lines. The interlayer insulating film is formed of an organic insulating film, and the contact layer of the TFT has a double layer structure of a fine crystal silicon (n.sup.+) layer and an amorphous silicon (n.sup.+) layer the crystal silicon (n.sup.+) layer being placed on the side closer to the source electrode and the drain electrode, and the amorphous silicon (n.sup.+) layer being placed on the opposite side. This improves both the ON characteristics and the OFF characteristics of the TFT are improved, and the stable operative region of the active matrix substrate and the margin to accommodate to variations in threshold value due to aging are expanded, without substantial additional production costs and a decrease in productivity.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: November 9, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katsuhiro Kawai, Shinya Yamakawa, Satoshi Yabuta, Atsushi Ban
  • Patent number: 5953583
    Abstract: A thin-film transistor of the reversed stagger type is provided with a gate electrode, first and second gate insulating films, a semiconductor layer, separated contact layers, and source electrodes and drain electrodes, all of which are stacked on a substrate. Upon manufacturing the thin-film transistor of this type, a gap section is pattered in a single contact-material layer. In this case, the contact-material layer is patterned by carrying out etching by the use of the source electrode and drain electrode as direct masks or by the use of a resist pattern that was used for forming the respective electrodes. Upon patterning a gap section in the contact-material layer between the source electrode and the drain electrode, no dedicated resist pattern is required; therefore, it is possible to reduce the number of the processes as compared with conventional manufacturing methods.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: September 14, 1999
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Atsushi Ban, Hisataka Suzuki, Masaya Okamoto