Abstract: A coding method intended to increase the error correction performance without greatly increasing the size of an error correction circuit, the method, as illustrated in FIG. 1A, includes the steps of dividing data constituting one page and yet to be coded into data blocks including a first data block located on one end of the one page to a fourth data block located on the other end of the one page; generating a first error correcting code by coding the first data block; generating a second error correcting code by coding a second data block and a part of the first data block in combination; generating a third error correcting code by coding a third data block and a part of the second data block in combination; and generating a fourth error correcting code by coding a fourth data block and a part of the third data block in combination.

Abstract: A coding method intended to increase the error correction performance without greatly increasing the size of an error correction circuit, the method, as illustrated in FIG. 1A, includes the steps of dividing data constituting one page and yet to be coded into data blocks including a first data block located on one end of the one page to a fourth data block located on the other end of the one page; generating a first error correcting code by coding the first data block; generating a second error correcting code by coding a second data block and a part of the first data block in combination; generating a third error correcting code by coding a third data block and a part of the second data block in combination; and generating a fourth error correcting code by coding a fourth data block and a part of the third data block in combination.

Abstract: A signal processing apparatus includes a first baseline wander correcting unit, provided in a processing path in which a predetermined processing is performed on an input signal, which corrects baseline wander by a feedforward and a second baseline wander correcting unit, provided anterior to the first baseline wander unit, which corrects the baseline wander by a feedback control. The first baseline wander correcting unit derives an amount of baseline wander. Further, it calculates a value corresponding to an average value of the amount of derived baseline wander and fine-adjusts a correction amount of baseline. Then it corrects the baseline wander by using the fine-adjusted baseline amount. The second baseline wander correcting unit calculates a value corresponding to an average value of the amount of baseline wander derived by the baseline wander derivation unit and coarse-adjusts a correction amount of baseline, and corrects the baseline wander by using the coarse-adjusted baseline amount.

Abstract: An error correction unit is an area in a page where the error bit count is low, and an error correction unit is an area in a page where the error bit count is high. The error correction unit includes a user data area, a first redundancy area, and a second redundancy area. The error correction unit includes a user data area, a first redundancy area, and a second redundancy area. Errors in the user data areas are corrected with a first set of redundant bits stored in the first redundancy areas, respectively. A second set of redundant bits for correcting errors in the user data area within the high-error bit count page is stored in the second redundancy area within the low-error bit count page and the second redundancy area within the high-error bit count page in a distributed manner.

Abstract: A read channel includes a variable gain amplifier, a low-pass filter, an AGC, an analog-to-digital converter, a frequency synthesizer, a filter, a soft-output detector, an LDPC decoding unit, a synchronizing signal detector, a run-length limited decoding unit, a descrambler, and a first baseline wander corrector. The first baseline wander corrector corrects a baseline variation by a feedforward control.

Abstract: In general, circuit scale in a DAE is large. The proposed DAE includes First multipliers, Unit processing circuits and Combined circuits. First multipliers use temporary estimated values to respectively compute signals. Unit processing circuits use the signals, which are multiplication results of the first multipliers, to respectively compute signals. Combined circuits use the signals, outputted from the unit processing circuits, to compute respective logarithm likelihood ratios ?4 and ?5. Here, in the unit processing circuits, by sharing part of circuits related to computing continuous ?s, the circuit scale of the DAE is reduced. For example, with regard to computation of ?4 and ?5, part of four unit processing circuits is shared.

Abstract: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. At least one of the plurality of baseline wander correcting units includes a correction permission control unit that controls permission or rejection of correction, and baseline wander in the input signal is corrected sequentially by each of the plurality of baseline wander correcting units, based on a control of the correction permission control unit. The baseline wander correcting unit corrects the baseline wander by determining whether or not the baseline correction is to be effected or not, so that the wander of baseline can be efficiently corrected.

Abstract: An LDPC unit decoder included in a signal decoding device is provided with a parity checking unit that is a multiplier for performing multiplication of a check matrix (parity check matrix) and temporary estimated values of an encoded signal, computed by a temporary estimated value computation unit. A check matrix holding unit holds the check matrix. If s and t are natural numbers, s?t?2, among s columns extracted from this check matrix, t columns or less have a linearly independent relationship. These s columns are multiplied at locations where error occurrence frequency is relatively high, with regard to the temporary estimated values. According to this mode, the matrix is composed to include t columns that are linearly independent, that is, t columns that are not linearly dependent.

Abstract: A general purpose of the present invention is to improve a DC-free property with a further reduced circuit scale while satisfying a run-length limit. An RLL/DC-free coding unit coding includes a first RLL coding unit, a first signal processing unit, a second RLL coding unit, and a DC component removal coding unit. The first RLL coding unit generates a first coded sequence by subjecting a digital signal sequence outputted from a scrambler to run-length limited coding. The first signal processing unit performs a predetermined signal processing on the digital signal sequence without changing the number of a plurality of bits contained in the digital signal sequence outputted from the scrambler 302. The second RLL coding unit generates a second coded sequence by subjecting the digital signal sequence, which is outputted from the first signal processing unit and on which the predetermined signal processing has been performed by the signal processing unit, to run-length limited coding.

Abstract: An LDPC encoder (304) includes a timing adjustment circuit (326) for performing timing adjustment on main data and outputting to a writing circuit (334), a parity generation circuit (328) for performing LDPC encoding on input signal series, generating the parity data, and outputting to the writing circuit (334), and the writing circuit (334) for sequentially receiving the main data and the parity data, and outputting to the storage apparatus via a write pre-compensation unit (305), a driver (306), and the like.

Abstract: An LDPC iteration decoder includes a second interleaver for performing interleave processing on a signal series outputted from a soft output detection unit, an LDPC decoder for implementing LDPC decoding processing on a signal that has undergone interleave processing; a checking unit for checking that an error has been corrected by the LDPC decoder; a second de-interleaver for performing sort processing the reverse of the second interleaver on a signal that has been LDPC decoded; a judging unit for judging whether to carry out iteration processing again; and a DAE for computing a likelihood again, in cases in which iteration decoding is carried out, and giving feedback to the front stage of the second interleaver.

Abstract: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. Baseline wander of the signal is corrected sequentially by each of the plurality of baseline wander correcting units. At least a baseline wander correcting unit placed in the initial stage may correct baseline wander by a feedback control. The baseline wander correcting units correct the baseline wanders, respectively, so that the wander of baseline can be efficiently corrected.

Abstract: A general purpose of the present invention is to improve a DC-free property with a further reduced circuit scale while satisfying a run-length limit. An RLL/DC-free coding unit coding includes a first RLL coding unit, a first signal processing unit, a second RLL coding unit, and a DC component removal coding unit. The first RLL coding unit generates a first coded sequence by subjecting a digital signal sequence outputted from a scrambler to run-length limited coding. The first signal processing unit performs a predetermined signal processing on the digital signal sequence without changing the number of a plurality of bits contained in the digital signal sequence outputted from the scrambler 302. The second RLL coding unit generates a second coded sequence by subjecting the digital signal sequence, which is outputted from the first signal processing unit and on which the predetermined signal processing has been performed by the signal processing unit, to run-length limited coding.

Abstract: A read channel includes a variable gain amplifier, a low-pass filter, an AGC, an analog-to-digital converter, a frequency synthesizer, a filter, a soft-output detector, an LDPC decoding unit, a synchronizing signal detector, a run-length limited decoding unit, a descrambler, and a first baseline wander corrector. The first baseline wander corrector corrects a baseline variation by a feedforward control.

Abstract: In general, a higher speed access storage device is desired. Proposed device relates to An LDPC iteration decoder. The LDPC iteration decoder (322) includes a second interleaver (350) for performing interleave processing on a signal series outputted from a soft output detection unit (320), an LDPC decoder (352) for implementing LDPC decoding processing on a signal that has undergone interleave processing; a checking unit (356) for checking that an error has been corrected by the LDPC decoder (352); a second de-interleaver (354) for performing sort processing the reverse of the second interleaver (350) on a signal that has been LDPC decoded; a judging unit (358) for judging whether to carry out iteration processing again; and a DAE (360) for computing a likelihood again, in cases in which iteration decoding is carried out, and giving feedback to the front stage of the second interleaver (350).

Abstract: In general, circuit scale in a DAE is large. The proposed DAE includes First multipliers (400 to 418), Unit processing circuits (420 to 430) and Combined circuits (432 and 434). First multipliers (400 to 418) use temporary estimated values (x0 to x9) to respectively compute signals (u0 to u9). Unit processing circuits (420 to 430) use the signals (u0 to u9), which are multiplication results of the first multipliers (400 to 418), to respectively compute signals (v4 to v9). Combined circuits (432 and 434) use the signals (v4 to v9), outputted from the unit processing circuits (420 to 430), to compute respective logarithm likelihood ratios ?4 and ?5. Here, in the unit processing circuits (420 to 430), by sharing part of circuits related to computing continuous ?s, the circuit scale of the DAE (338) is reduced. For example, with regard to computation of ?4 and ?5, part of four unit processing circuits (422, 424, 426, and 428) is shared.

Abstract: An LDPC encoder (304) includes a timing adjustment circuit (326) for performing timing adjustment on main data and outputting to a writing circuit (334), a parity generation circuit (328) for performing LDPC encoding on input signal series, generating the parity data, and outputting to the writing circuit (334), and the writing circuit (334) for sequentially receiving the main data and the parity data, and outputting to the storage apparatus via a write pre-compensation unit (305), a driver (306), and the like.

Abstract: A signal processing apparatus has a plurality of baseline wander correcting units, provided in a processing path in which a predetermined processing is performed on an input signal. At least one of the plurality of baseline wander correcting units includes a correction permission control unit that controls permission or rejection of correction, and baseline wander in the input signal is corrected sequentially by each of the plurality of baseline wander correcting units, based on a control of the correction permission control unit. The baseline wander correcting unit corrects the baseline wander by determining whether or not the baseline correction is to be effected or not, so that the wander of baseline can be efficiently corrected.

Abstract: An LDPC unit decoder included in a signal decoding device is provided with a parity checking unit that is a multiplier for performing multiplication of a check matrix (parity check matrix) and temporary estimated values of an encoded signal, computed by a temporary estimated value computation unit. A check matrix (parity check matrix) holding unit holds the check matrix (parity check matrix). If s and t are natural numbers, s?t?2, among s columns extracted from this check matrix (parity check matrix), t columns or less have a linearly independent relationship. These s columns are multiplied at locations where error occurrence frequency is relatively high, with regard to the temporary estimated values. According to this mode, the matrix is composed to include t columns that are linearly independent, that is, t columns that are not linearly dependent.

Abstract: A baseline wander correcting unit is provided in a processing path in which a predetermined processing is performed on an input signal. The baseline wander correcting unit includes a baseline wander derivation unit which derives an amount of wander of baseline of a signal on which the predetermined processing has been performed, and an adjustment unit which adjusts an amount of wander of the baseline derived by the baseline wander derivation unit and outputs a baseline correction amount, so that the baseline wander correcting unit corrects the baseline wander by a feedforward control. The correction by the feedforward control ensures the baseline wander in the event of an instantaneous wander.