Patents by Inventor Atsushi Fujiki
Atsushi Fujiki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8570617Abstract: An image reading apparatus includes an image reader, an image adjuster and an execution controller that causes the image reader to read an adjustment document and causes the image adjuster to adjust image data generated by the image reader. The adjustment document includes line images and parameter images at positions spaced apart in a main scanning direction in a margin area where the line images are not provided. The parameter images indicate parameters used in image adjustment processing. The execution controller judges whether the image data corresponding to predetermined positions in the main scanning direction coincide, selects one of the image data judged to coincide, and causes the image adjuster to perform the image adjustment using the selected image data and the parameter indicated by the image data generated by reading the parameter image at the position in the main scanning direction of the selected image data.Type: GrantFiled: October 31, 2011Date of Patent: October 29, 2013Assignee: Kyocera Mita CorporationInventors: Yasuyuki Yabuuchi, Atsushi Fujiki, Masaki Baba
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Patent number: 8564112Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.Type: GrantFiled: October 19, 2012Date of Patent: October 22, 2013Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Atsushi Fujiki, Tatsuhiro Seki, Nobuya Koike, Yukihiro Sato, Kisho Ashida
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Patent number: 8441065Abstract: A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps.Type: GrantFiled: August 5, 2010Date of Patent: May 14, 2013Assignee: Renesas Electronics CorporationInventors: Hirokatsu Suzuki, Atsushi Fujiki, Yoshito Nakazawa
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Publication number: 20130082334Abstract: A semiconductor device is improved in reliability. A switching power MOSFET and a sense MOSFET for sensing a current flowing in the power MOSFET, which is smaller in area than the power MOSFET, are formed in one semiconductor chip. The semiconductor chip is mounted over a chip mounting portion via a conductive bonding material, and sealed in a resin. Over the main surface of the semiconductor chip, a metal plate is bonded to a source pad electrode of the power MOSFET. In the plan view, the metal plate does not overlap a sense MOSFET region where the sense MOSFET is formed. The metal plate is bonded to the source pad electrode so as to surround three of the sides of the sense MOSFET region.Type: ApplicationFiled: September 12, 2012Publication date: April 4, 2013Inventors: Hiroyuki NAKAMURA, Yukihiro Sato, Atsushi Fujiki, Tatsuhiro Seki
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Patent number: 8299599Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.Type: GrantFiled: March 3, 2011Date of Patent: October 30, 2012Assignee: Renesas Electronics CorporationInventors: Hiroyuki Nakamura, Atsushi Fujiki, Tatsuhiro Seki, Nobuya Koike, Yukihiro Sato, Kisho Ashida
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Publication number: 20120261825Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: ApplicationFiled: June 26, 2012Publication date: October 18, 2012Inventors: Nobuya KOIKE, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
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Patent number: 8232629Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: GrantFiled: August 20, 2007Date of Patent: July 31, 2012Assignee: Renesas Electronics CorporationInventors: Nobuya Koike, Atsushi Fujiki, Norio Kido, Yukihiro Sato, Hiroyuki Nakamura
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Publication number: 20120133996Abstract: An image reading apparatus includes an image reader, an image adjuster and an execution controller that causes the image reader to read an adjustment document and causes the image adjuster to adjust image data generated by the image reader. The adjustment document includes line images and parameter images at positions spaced apart in a main scanning direction in a margin area where the line images are not provided. The parameter images indicate parameters used in image adjustment processing. The execution controller judges whether the image data corresponding to predetermined positions in the main scanning direction coincide, selects one of the image data judged to coincide, and causes the image adjuster to perform the image adjustment using the selected image data and the parameter indicated by the image data generated by reading the parameter image at the position in the main scanning direction of the selected image data.Type: ApplicationFiled: October 31, 2011Publication date: May 31, 2012Applicant: KYOCERA MITA CORPORATIONInventors: Yasuyuki Yabuuchi, Atsushi Fujiki, Masaki Baba
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Patent number: 8114710Abstract: The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip.Type: GrantFiled: January 23, 2009Date of Patent: February 14, 2012Assignee: Renesas Electronics CorporationInventors: Akira Muto, Nobuya Koike, Katsuo Arai, Atsushi Fujiki
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Publication number: 20110215400Abstract: To improve the performance and reliability of semiconductor devices. For the semiconductor chip CP1, power MOSFETs Q1 and Q2 for the switch, a diode DD1 for detecting the heat generation of the power MOSFET Q1, a diode DD2 for detecting the heat generation of the power MOSFET Q2, and plural pad electrodes PD are formed. The power MOSFET Q1 and the diode DD1 are arranged in a first MOSFET region RG1 on the side of a side SD1, and the power MOSFET Q2 and the diode DD2 are arranged in a second MOSFET region RG2 on the side of a side SD2. The diode DD1 is arranged along the side SD1, the diode DD2 is arranged along the side SD2, and all pad electrodes PD other than the pad electrodes PDS1 and PDS2 for the source are arranged along a side SD3 between the diodes DD1 and DD2.Type: ApplicationFiled: March 3, 2011Publication date: September 8, 2011Inventors: Hiroyuki NAKAMURA, Atsushi FUJIKI, Tatsuhiro SEKI, Nobuya KOIKE, Yukihiro SATO, Kisho ASHIDA
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Publication number: 20100315751Abstract: A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps.Type: ApplicationFiled: August 5, 2010Publication date: December 16, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Hirokatsu Suzuki, Atsushi Fujiki, Yoshito Nakazawa
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Publication number: 20100308421Abstract: The size of a semiconductor device is reduced. A semiconductor chip in which a power MOSFET is placed above a semiconductor chip in which another power MOSFET is formed and they are sealed with an encapsulation resin portion. The semiconductor chips are so arranged that the upper semiconductor chip does not overlap with the area positioned directly above a gate pad electrode of the lower semiconductor chip. The semiconductor chips are identical in size and the respective source pad electrodes and gate pad electrodes of the lower semiconductor chip and the upper semiconductor chip are identical in shape and arrangement. The lower semiconductor chip and the upper semiconductor chip are arranged with their respective centers displaced from each other.Type: ApplicationFiled: April 26, 2010Publication date: December 9, 2010Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Akira MUTO, Yuichi MACHIDA, Nobuya KOIKE, Atsushi FUJIKI, Masaki TAMURA
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Publication number: 20090215230Abstract: The radiation performance of a resin sealed semiconductor package is enhanced and further the fabrication yield thereof is enhanced. A drain terminal coupled to the back surface drain electrode of a semiconductor chip is exposed at the back surface of an encapsulation resin section. Part of the following portion and terminal is exposed at the top surface of the encapsulation resin section: the first portion of a source terminal coupled to the source pad electrode of the semiconductor chip and a gate terminal coupled to the gate pad electrode of the semiconductor chip. The remaining part of the second portion of the source terminal and the gate terminal is exposed at the back surface of the encapsulation resin section. When this semiconductor device is manufactured, bonding material and a film member are placed between the drain terminal and the semiconductor chip.Type: ApplicationFiled: January 23, 2009Publication date: August 27, 2009Inventors: Akira MUTO, Nobuya Koike, Katsuo Arai, Atsushi Fujiki
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Patent number: 7482861Abstract: A power MOSFET Qp and a protection circuit 3 are formed over a semiconductor substrate to constitute a construction in which the power MOSFET Qp and the protection circuit 3 are electrically separated from each other. Then, a screening voltage is applied between the gate electrode and the source electrode of the power MOSFET Qp which is electrically separated from the protection circuit 3, thereby eliminating a power MOSFET Qp having a latent defect. Subsequently, a non-defective power MOSFET Qp and the protection circuit 3 are electrically connected by a bonding wire.Type: GrantFiled: August 28, 2000Date of Patent: January 27, 2009Assignee: Hitachi, Ltd.Inventors: Atsushi Fujiki, Tetsuo Iijima
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Publication number: 20080054422Abstract: It is made for the layout of the mounting wiring at the time of mounting to become efficient by changing the structure of a semiconductor device. A first chip is mounted on a first die pad, and a second chip is also mounted on a second die pad. A first die pad and a second die pad do division structure in parallel to the first side and second side of sealing body 40. As a result, the pin for an output from a first chip and the pin for control of the circuit for a drive can make it able to project from a counter direction, and can set the wiring layout at the time of mounting as the minimum route.Type: ApplicationFiled: August 20, 2007Publication date: March 6, 2008Inventors: Nobuya KOIKE, Atsushi FUJIKI, Norio KIDO, Yukihiro SATO, Hiroyuki NAKAMURA
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Publication number: 20070138566Abstract: A semiconductor device which combines reliability and the guarantee of electrical characteristics is provided. A power MOSFET and a protection circuit formed over the same semiconductor substrate are provided. The power MOSFET is a trench gate vertical type P-channel MOSFET and the conduction type of the gate electrode is assumed to be P-type. The protection circuit includes a planar gate horizontal type offset P-channel MOSFET and the conduction type of the gate electrode is assumed to be N-type. These gate electrode and gate electrode are formed in separate steps.Type: ApplicationFiled: December 14, 2006Publication date: June 21, 2007Inventors: Hirokatsu Suzuki, Atsushi Fujiki, Yoshito Nakazawa
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Publication number: 20050286194Abstract: The object of the invention is to protect a power MOS transistor using a transistor having trench structure from overcurrent and to enhance the reliability. To achieve the object, a power MOS transistor, a transistor for detecting current for detecting the current of the power MOS transistor and generating a detection signal supplied to an external control circuit and devices configuring a protection circuit for detecting the current of the power MOS transistor and inhibiting current by forcedly dropping the gate voltage of the power MOS transistor when current equal to or exceeding a predetermined value flows are provided in the same semiconductor chip.Type: ApplicationFiled: April 22, 2005Publication date: December 29, 2005Inventors: Atsushi Fujiki, Masatoshi Nakasu
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Patent number: 6496049Abstract: This semiconductor integrated circuit is constituted by any one of a p-channel MOS transistor and an n-channel MOS transistor, and is connected between the control terminal and the common terminal so as to produce predetermined voltage. The comparing circuit is operated in response to a control voltage applied between the control terminal and the common terminal so as to compare the predetermined reference voltage with the current-detected voltage which is obtained from the current detecting circuit. The gate controlling MOS transistor controls a gate voltage of the power MOS transistor based upon the comparison output of the comparing circuit. Then, all of these structural members are formed on the same semiconductor substrate.Type: GrantFiled: July 19, 2001Date of Patent: December 17, 2002Assignee: Hitachi, Ltd.Inventors: Nobuo Tsukagoshi, Masatoshi Nakasu, Atsushi Fujiki, Kazuaki Ohsawa
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Publication number: 20020017941Abstract: This semiconductor integrated circuit is constituted by any one of a p-channel MOS transistor and an n-channel MOS transistors and is connected between the control terminal and the common terminal so as to produce predetermined voltage. The comparing circuit is operated in response to a control voltage applied between the control terminal and the common terminal so as to compare the predetermined reference voltage with the current-detected voltage which is obtained from the current detecting circuit. The gate controlling MOS transistor controls a gate voltage of the power MOS transistor based upon the comparison output of the comparing circuit. Then, all of these structural members are formed on the same semiconductor substrate.Type: ApplicationFiled: July 19, 2001Publication date: February 14, 2002Inventors: Nobuo Tsukagoshi, Masatoshi Nakasu, Atsushi Fujiki, Kazuaki Ohsawa
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Patent number: 6218889Abstract: A power MOSFET Qp and a protection circuit 3 are formed over a semiconductor substrate to constitute a construction in which the power MOSFET Qp and the protection circuit 3 are electrically separated from each other. Then, a screening voltage is applied between the gate electrode and the source electrode of the power MOSFET Qp which is electrically separated from the protection circuit 3, thereby eliminating a power MOSFET Qp having a latent defect. Subsequently, a non-defective power MOSFET Qp and the protection circuit 3 are electrically connected by a bonding wire.Type: GrantFiled: December 8, 1998Date of Patent: April 17, 2001Assignee: Hitachi, Ltd.Inventors: Atsushi Fujiki, Tetsuo Iijima