Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate, and insulating layer on the semiconductor substrate, a plurality of contact plugs in the insulating layer, and an insulating layer where capacitors, a plurality of contact plugs, barrier metal layers and copper interconnections are formed. Source/drain regions in the upper surface of the semiconductor substrate are electrically connected to the copper interconnections. One of adjacent source/drain regions in the upper surface of the semiconductor substrate is electrically connected to the copper interconnection, while the other is electrically connected to the capacitor.

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

Abstract: An isolation film is formed in a surface of a substrate 1 in which active regions are formed, to separate the active regions from each other. Subsequently, a portion of the isolation film is removed, to form a recess, which is then filled with a portion of an upper electrode. Also, an insulating film 8 is interposed between the upper electrode and the substrate.

Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Abstract: A semiconductor device includes a diffusion region in a semiconductor substrate, a gate insulation film on the semiconductor substrate, a gate electrode on the gate insulation film, an interlayer insulation film on the semiconductor substrate covering the gate electrode, and a capacitor on the interlayer insulation film. The capacitor includes a laminated structure made up of a lower electrode, a dielectric film, and an upper electrode. The diffusion region, the gate electrode, and the lower electrode are connected to one another by a common contact in the interlayer insulation film.

Abstract: A plurality of gate electrodes is formed on a semiconductor substrate having a DRAM area and a logic area. Next, sidewalls, each of which includes a silicon nitride film covering the sides of gate electrodes and a silicon oxide film covering the silicon nitride film, are formed on the sides of the gate electrodes respectively. After formation of a transistor having an LDD structure in the logic area, the silicon oxide film formed on the sides of the gate electrodes is removed by wet etching. Next, a silicon nitride film is formed on the whole surface of the semiconductor substrate, and an interlayer dielectric is formed on the silicon nitride film.

Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Abstract: A semiconductor device comprises a diffusion layer in a semiconductor substrate, a gate insulation film on the semiconductor substrate, a gate electrode on the gate insulation film, an interlayer insulation film on the semiconductor substrate so as to cover the gate electrode, and a capacitor on the interlayer insulation film. The capacitor includes a laminated structure made up of a lower electrode, a dielectric film, and an upper electrode. The diffusion layers, the gate electrode, and the lower electrode are connected to one another by a common contact in the interlayer insulation film.

Abstract: A technique for enhancing the performance of a memory- and logic-equipped semiconductor device is provided. The semiconductor device comprises a semiconductor substrate (1), an insulating layer (19) on the semiconductor substrate (1), a plurality of contact plugs (16, 66) in the insulating layer (19), and an insulating layer (30) where capacitors (82), a plurality of contact plugs (25, 75), barrier metal layers (27, 87) and copper interconnections (29, 88) are formed. Source/drain regions (9) in the upper surface of the semiconductor substrate (1) are electrically connected to the copper interconnections (29). One of adjacent source/drain regions (59) in the upper surface of the semiconductor substrate (1) is electrically connected to the copper interconnection (88), while the other is electrically connected to the capacitor (82).

Abstract: A technique for making it possible to miniaturize a semiconductor device having a memory device and a logic device on one semiconductor substrate even when a self-aligned process can not be utilized, i.e., a contact hole can not be self-aligned to a gate electrode. Contact holes (15, 65) are formed in an insulating layer (19) such that the contact holes (15) are located beside gate electrodes 6 while the contact holes (65) are located beside gate electrodes (56). An insulating film 35 is formed on each side face of the contact holes (15, 65). Then, contact plugs (16) filling the contact holes (15) and contact plugs (66) filling the contact holes (65) are formed.

Abstract: In the semiconductor device, in order to meet the demand of reduced diameter of a contact hole along with the miniaturization of the semiconductor device, an anti-HF side wall film which is not etched by a hydrofluoric acid, formed of an isolating film such as nitride film, is provided on the side wall of contact hole. Further, a second impurity region which is connected to one of the pair of n type source/drain regions and a first impurity region reaching a p type isolation region are provided in silicon substrate 1 near the lower end of contact hole. Because of this structure, it becomes possible to prevent expansion of the diameter for forming the interconnection layer, as desired in the miniaturized semiconductor device, and therefore a semiconductor device and manufacturing method thereof which stabilize operation characteristic of the semiconductor device can be provided.

Abstract: In a semiconductor exposure apparatus (10), four blinds (3a-3d) movable back and forth in the horizontal direction are provided on a path of light (L), to allow an irradiated region with light (L) on a mask (4) to be limited to an arbitrary rectangular region. On the other hand, a plurality of mask patterns different from each other are formed on the mask (4). When exposing one of the patterns, the blinds (3a-3d) are arranged such that the irradiated region with light (L) is positioned only over the one of the patterns and the periphery of the one of the patterns is shielded. This allows the plurality of mask patterns to be exposed with the single mask (4), achieving a reduction in costs for mask manufacturing and manufacturing time.

Abstract: It is an object to provide a semiconductor technique for shortening a time required for manufacturing a semiconductor device of a memory and logic mixing type. Contact plugs (17) and (67) are formed in an interlayer insulating film (14) and stopper films (13) and (15) with an upper surface thereof exposed from the stopper film (15). Then, an interlayer insulating film (18) is formed on the stopper film (15) and the contact plugs (17) and (67), and an opening portion (69) for exposing the contact plug (67) is formed in the interlayer insulating film (18). By etching only the interlayer insulating film (18) without etching the stopper film (15), the opening portion (69) can be formed. Consequently, it is possible to shorten a time required for forming the opening portion (69).