Patents by Inventor Atsushi HACHIYA
Atsushi HACHIYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971641Abstract: An active matrix substrate includes a first TFT disposed in each of pixel regions, a first flattened layer covering the first TFT, and a pixel electrode provided on the first flattened layer. The first TFT includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The active matrix substrate further includes a first connection electrode for electrically connecting a drain contact region of the oxide semiconductor layer and the pixel electrode. The first flattened layer includes a pixel contact hole formed so as to expose a part of the first connection electrode. The bottom face of the pixel contact hole at least partially overlaps, of a lower gate metal layer including a lower gate electrode and an upper gate metal layer including an upper gate electrode, at least the lower gate metal layer when viewed from the normal direction of the substrate.Type: GrantFiled: November 1, 2022Date of Patent: April 30, 2024Assignee: Sharp Display Technology CorporationInventors: Atsushi Hachiya, Hiroaki Furukawa, Yuhichi Saitoh, Kuniaki Okada
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Patent number: 11955558Abstract: One conductor region of a crystalline silicon semiconductor layer in a first transistor is electrically connected to one conductor region of an oxide semiconductor layer in a second transistor through a first contact hole and a second contact hole communicating with each other.Type: GrantFiled: April 26, 2019Date of Patent: April 9, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Atsushi Hachiya, Hiroaki Furukawa, Yuhichi Saitoh, Tomohisa Aoki
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Publication number: 20240085752Abstract: An active matrix substrate includes: a thin film transistor located in each pixel region; and a pixel electrode electrically coupled with the thin film transistor. The thin film transistor includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The width of an upper gate line electrically coupled with the upper gate electrode is greater than the width of a lower gate line electrically coupled with the lower gate electrode.Type: ApplicationFiled: August 24, 2023Publication date: March 14, 2024Inventors: Atsushi HACHIYA, Hiroaki FURUKAWA, Yuhichi SAITOH
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Publication number: 20230209893Abstract: A display device includes a pixel circuit and a light-emitting element, the pixel circuit including: a transistor with a first structure including a crystalline silicon semiconductor film and a first gate electrode; and a transistor with a second structure including an oxide semiconductor film and a second gate electrode, the display device further includes: a first interlayer insulation film; and a second interlayer insulation film, wherein the pixel circuit includes: a drive transistor that has the first structure: and a capacitive element, the capacitive element includes: a first capacitor electrode electrically connected to a first gate electrode of the drive transistor; a second capacitor electrode opposite the first capacitor electrode; and a dielectric film between the first capacitor electrode and the second capacitor electrode, and the dielectric film is disposed in a different layer than are the first interlayer insulation film and the second interlayer insulation film.Type: ApplicationFiled: May 25, 2020Publication date: June 29, 2023Inventors: Tomohisa AOKI, ATSUSHI HACHIYA, Yuhichi SAITOH, HIROAKI FURUKAWA
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Publication number: 20230168550Abstract: An active matrix substrate includes a substrate, a pixel TFT that is supported by the substrate, provided corresponding to each of a plurality of pixel areas, and includes an oxide semiconductor layer, an organic insulating layer disposed above at least the oxide semiconductor layer of the pixel TFT, and an inorganic insulating layer disposed in contact with an upper surface of the organic insulating layer on the organic insulating layer. The organic insulating layer and the inorganic insulating layer are provided with a plurality of dual-layer hole structure portions, each of the dual-layer hole structure portions includes a through-hole provided in the inorganic insulating layer and a bottomed hole provided in the organic insulating layer and positioned below the through-hole, and the through-hole is positioned on an inner side of an outer edge of the bottomed hole when viewed from a normal direction of the substrate.Type: ApplicationFiled: November 29, 2022Publication date: June 1, 2023Inventors: Yuhichi SAITOH, Hiroaki FURUKAWA, Atsushi HACHIYA, Hiroshi MATSUKIZONO
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Publication number: 20230161210Abstract: An active matrix substrate includes a first TFT disposed in each of pixel regions, a first flattened layer covering the first TFT, and a pixel electrode provided on the first flattened layer. The first TFT includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The active matrix substrate further includes a first connection electrode for electrically connecting a drain contact region of the oxide semiconductor layer and the pixel electrode. The first flattened layer includes a pixel contact hole formed so as to expose a part of the first connection electrode. The bottom face of the pixel contact hole at least partially overlaps, of a lower gate metal layer including a lower gate electrode and an upper gate metal layer including an upper gate electrode, at least the lower gate metal layer when viewed from the normal direction of the substrate.Type: ApplicationFiled: November 1, 2022Publication date: May 25, 2023Inventors: Atsushi HACHIYA, Hiroaki FURUKAWA, Yuhichi SAITOH, Kuniaki OKADA
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Patent number: 11577245Abstract: An electrowetting device includes a first substrate, a plurality of first electrodes formed on the first substrate, a dielectric layer formed on the plurality of first electrodes, a first water-repellent layer formed on the dielectric layer, a second substrate, a second electrode formed on the second substrate, and a second water-repellent layer formed on the second electrode. The first substrate and the second substrate are arranged with a gap between the first water-repellent layer and the second water-repellent layer. The first electrode includes an indium oxide-zinc oxide layer, the dielectric layer includes a silicon nitride layer, and the silicon nitride layer is formed directly on the indium oxide-zinc oxide layer.Type: GrantFiled: September 6, 2019Date of Patent: February 14, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Chihiro Tachino, Kazuya Tsujino, Atsushi Hachiya
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Patent number: 11550196Abstract: A display device in the present disclosure includes the following: a substrate; a plurality of source bus lines extending in a first direction above the substrate; a plurality of semiconductor layers extending in the first direction above the plurality of source bus lines; and a first groove-shaped recess extending in a second direction crossing the first direction, the first groove-shaped recess constituting a first contact hole extending from above the plurality of source bus lines to the plurality of source bus lines. Each of the plurality of semiconductor layers is disposed along a surface of the first groove-shaped recess so as to cross the first groove-shaped recess, and each of the plurality of semiconductor layers is electrically connected to each of the plurality of source bus lines on the bottom surface of the first groove-shaped recess.Type: GrantFiled: February 15, 2022Date of Patent: January 10, 2023Assignee: SHARP KABUSHIKI KAISHAInventors: Kuniaki Okada, Atsushi Hachiya
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Publication number: 20220291559Abstract: A display device in the present disclosure includes the following: a substrate; a plurality of source bus lines extending in a first direction above the substrate; a plurality of semiconductor layers extending in the first direction above the plurality of source bus lines; and a first groove-shaped recess extending in a second direction crossing the first direction, the first groove-shaped recess constituting a first contact hole extending from above the plurality of source bus lines to the plurality of source bus lines. Each of the plurality of semiconductor layers is disposed along a surface of the first groove-shaped recess so as to cross the first groove-shaped recess, and each of the plurality of semiconductor layers is electrically connected to each of the plurality of source bus lines on the bottom surface of the first groove-shaped recess.Type: ApplicationFiled: February 15, 2022Publication date: September 15, 2022Inventors: KUNIAKI OKADA, ATSUSHI HACHIYA
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Publication number: 20220209021Abstract: A crystalline silicon semiconductor layer includes a first channel region and a second conductor region. An oxide semiconductor layer includes a second channel region and a second conductor region. An lower metal layer includes a lower wire. The lower wire is in contact with a first conductor region in a first contact hole. The first conductor region and the second conductor region are electrically connected together through the lower wire.Type: ApplicationFiled: April 26, 2019Publication date: June 30, 2022Inventors: HIROAKI FURUKAWA, Yuhichi SAITOH, Tomohisa AOKI, ATSUSHI HACHIYA
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Publication number: 20220209020Abstract: An oxide semiconductor layer includes a second channel region and a second conductor region. The lower metal layer includes a contact wire in contact with the second conductor region. The upper metal layer includes an upper wire. A second interlayer insulating film is provided with a second contact hole overlapping an upper wire and the contact wire. The second conductor region and the upper wire electrically connect together through the contact wire.Type: ApplicationFiled: April 26, 2019Publication date: June 30, 2022Inventors: Tomohisa AOKI, HIROAKI FURUKAWA, Yuhichi SAITOH, ATSUSHI HACHIYA
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Publication number: 20220157996Abstract: One conductor region of a crystalline silicon semiconductor layer in a first transistor is electrically connected to one conductor region of an oxide semiconductor layer in a second transistor through a first contact hole and a second contact hole communicating with each other.Type: ApplicationFiled: April 26, 2019Publication date: May 19, 2022Inventors: ATSUSHI HACHIYA, HIROAKI FURUKAWA, Yuhichi SAITOH, Tomohisa AOKI
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Patent number: 11264235Abstract: Provided are an active matrix substrate having a reduced driving voltage and excellent adhesion between a dielectric layer and a water-repellent layer and a microfluidic device including the substrate. The active matrix substrate includes an array electrode, a dielectric layer covering the array electrode, and a first water-repellent layer in this order on a first substrate. The dielectric layer includes a silicon nitride film located on the side in contact with the first water-repellent layer, and the silicon nitride film has a surface layer region containing oxygen in the surface on the side in contact with the first water-repellent layer.Type: GrantFiled: July 27, 2018Date of Patent: March 1, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Kazuya Tsujino, Tomoko Teranishi, Atsushi Hachiya, Hiroaki Furukawa
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Patent number: 11217610Abstract: An active matrix substrate includes: a first substrate; and first electrodes, a dielectric layer covering the first electrodes, and a first water-repelling layer in this sequence on the first substrate, wherein the dielectric layer has a multilayer structure including two or more layers and includes a silicon nitride film and a metal-oxide film between the silicon nitride film and the first water-repelling layer, and the silicon nitride film has an oxygen-containing surface layer region on a surface thereof that is in contact with the metal-oxide film.Type: GrantFiled: March 27, 2020Date of Patent: January 4, 2022Assignee: SHARP KABUSHIKI KAISHAInventors: Atsushi Hachiya, Hiroaki Furukawa, Kazuya Tsujino
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Publication number: 20210134585Abstract: Provided are an active matrix substrate having a reduced driving voltage and excellent adhesion between a dielectric layer and a water-repellent layer and a microfluidic device including the substrate. The active matrix substrate includes an array electrode, a dielectric layer covering the array electrode, and a first water-repellent layer in this order on a first substrate. The dielectric layer includes a silicon nitride film located on the side in contact with the first water-repellent layer, and the silicon nitride film has a surface layer region containing oxygen in the surface on the side in contact with the first water-repellent layer.Type: ApplicationFiled: July 27, 2018Publication date: May 6, 2021Inventors: KAZUYA TSUJINO, TOMOKO TERANISHI, ATSUSHI HACHIYA, HIROAKI FURUKAWA
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Patent number: 10854756Abstract: An active matrix substrate includes a demultiplexer circuit which includes multiple TFTs. Each TFT includes a gate electrode, an oxide semiconductor layer that includes a source contact area, a drain contact area, and an area between a source and a drain that includes a channel region, a channel protection layer that covers only a portion of the area between the source and the drain, a source electrode that is brought into contact with the source contact area, and a drain electrode that is brought into contact with the drain contact area. At a cross-section in a channel length direction, of each TFT, an end portion facing toward the channel region, of one of the source and drain electrodes is brought into contact with the channel protection layer, and an end portion facing toward the channel region, of the other is positioned at a distance away from the channel protection layer.Type: GrantFiled: March 1, 2019Date of Patent: December 1, 2020Assignee: SHARP KABUSHIKI KAISHAInventors: Yuhichi Saitoh, Hiroaki Furukawa, Tomohisa Aoki, Atsushi Hachiya
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Publication number: 20200312889Abstract: An active matrix substrate includes: a first substrate; and first electrodes, a dielectric layer covering the first electrodes, and a first water-repelling layer in this sequence on the first substrate, wherein the dielectric layer has a multilayer structure including two or more layers and includes a silicon nitride film and a metal-oxide film between the silicon nitride film and the first water-repelling layer, and the silicon nitride film has an oxygen-containing surface layer region on a surface thereof that is in contact with the metal-oxide film.Type: ApplicationFiled: March 27, 2020Publication date: October 1, 2020Inventors: ATSUSHI HACHIYA, HIROAKI FURUKAWA, KAZUYA TSUJINO
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Publication number: 20200099014Abstract: A method of producing an element substrate includes (A) a process of forming a transparent electrode film containing a transparent metal oxide on an upper side of an insulating film located above a conductive film, (B) a process of forming a photoresist film on an upper side of the transparent electrode film and patterning the photoresist film, (C) a process of removing a portion of the transparent electrode film not covered by the photoresist film to form an opening H extending through the transparent electrode film, and (D) a process of removing a portion of the insulating film not covered by the photoresist film and the transparent electrode film to form a contact hole extending to the conductive film. The element substrate produced by the method includes an electrode including the transparent electrode film electrically connected to the conductive film at the contact hole.Type: ApplicationFiled: September 6, 2019Publication date: March 26, 2020Inventors: Atsushi HACHIYA, Hiroaki FURUKAWA
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Publication number: 20200078790Abstract: An electrowetting device includes a first substrate, a plurality of first electrodes formed on the first substrate, a dielectric layer formed on the plurality of first electrodes, a first water-repellent layer formed on the dielectric layer, a second substrate, a second electrode formed on the second substrate, and a second water-repellent layer formed on the second electrode. The first substrate and the second substrate are arranged with a gap between the first water-repellent layer and the second water-repellent layer. The first electrode includes an indium oxide-zinc oxide layer, the dielectric layer includes a silicon nitride layer, and the silicon nitride layer is formed directly on the indium oxide-zinc oxide layer.Type: ApplicationFiled: September 6, 2019Publication date: March 12, 2020Inventors: CHIHIRO TACHINO, KAZUYA TSUJINO, ATSUSHI HACHIYA
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Publication number: 20190273167Abstract: An active matrix substrate includes a demultiplexer circuit which includes multiple TFTs. Each TFT includes a gate electrode, an oxide semiconductor layer that includes a source contact area, a drain contact area, and an area between a source and a drain that includes a channel region, a channel protection layer that covers only a portion of the area between the source and the drain, a source electrode that is brought into contact with the source contact area, and a drain electrode that is brought into contact with the drain contact area. At a cross-section in a channel length direction, of each TFT, an end portion facing toward the channel region, of one of the source and drain electrodes is brought into contact with the channel protection layer, and an end portion facing toward the channel region, of the other is positioned at a distance away from the channel protection layer.Type: ApplicationFiled: March 1, 2019Publication date: September 5, 2019Inventors: Yuhichi SAITOH, Hiroaki FURUKAWA, Tomohisa AOKI, Atsushi HACHIYA