Abstract: An electronic circuit including, a plurality of memory masters that access a memory, and an arbitration circuit that arbitrates between the plurality of memory masters requesting access to the memory. The arbitration circuit performs the following processing, when one of the plurality of memory masters has succeeded in accessing the memory, priority of the one memory master is decreased, and priority of the other one of the plurality of masters is increased, for each of the plurality of memory masters, a correction value to be applied to the priority is determined according to the number of accesses made to the memory during a certain past period, and permission to access the memory is granted to a memory master selected from along the plurality of memory masters according to the priority corrected by adding the correction value.

Abstract: A digital circuit design assist system is directed to provide a system which independently verifies hardware divided into a plurality of units or the hardware and software, and reduces the design time. The system includes a functional model storage unit 1 for storing functional models in order to design hardware for a desired digital circuit including the hardware alone or the hardware and firmware, and functionally expressing the digital circuit by a hardware description language through a text editor 15 by coding input. Logic synthesis system 2 is provided for converting the functional model to a structural model, structurally expressed by the hardware description language. Structural model storage unit 3 is provided for storing the structural model, and a language model library storage unit 4 is provided for storing language models each expressing each of a plurality of components constituting the hardware by the hardware description language.