Abstract: Since centers of a second gear, a fourth gear and a sixth gear coincide with each other and are disposed rotatably round a circumference of the same long shaft, a compact configuration can be realized while using a gear train of five gears to obtain a reduction gear ratio of a high gear ratio. The configuration in which the three gears have the same rotational center shaft in the way described above in an actuator which incorporates a plurality of gears is advantageous in that the number of center shafts is reduced and that the number of supporting holes in a housing which support center shafts is reduced.

Abstract: An amide derivative represented by the following Formula (1) is provided as an amide derivative showing a significantly excellent effect for a pest control action. In the following Formula (1), A represents a carbon atom, a nitrogen atom, or the like, and K represents a non-metal atomic group necessary for forming a cyclic linking group derived from benzene or a heterocyclie. X represents a halogen atom or the like; n represents an integer of from 0 to 4. R1 and R2 represent hydrogen atoms, alkyl groups, or the like. T represents —C(=G1)-Q1 or —C(=G1)-G2Q2, and G1 to G3 each represent oxygen atoms or the like. Q1 and Q2 each represent a hydrogen atom, an alkyl group, an aryl group, or the like. Y1 and Y5 each represent a halogen atom or the like, Y2 and Y4 each represent a hydrogen atom or the like, and Y3 represents a C2-C5 haloalkyl group.

Abstract: A pest control agent containing a compound represented by the following Formula (1), wherein A represents a carbon atom, a nitrogen atom, or the like, K represents a non-metal atom group necessary for forming a cyclic linking group derived from a 5- or 6-membered aromatic ring, in combination with A and two carbon atoms to which A bonds, X represents a hydrogen atom, a halogen atom, or the like, n represents an integer of from 0 to 4, T represents —C(=G1)-Q1 (wherein G1 and G2 represent an oxygen atom or the like, Q1 represents a phenyl group which may have a substituent, a heterocyclic group which may have a substituent, or the like), or the like, Q2 represents a phenyl group or the like, G3 represents an oxygen atom or the like, and R1 and R2 each independently represent a hydrogen atom, a C1-C6 alkyl group, or a group represented by -L-D, or the like (provided that at least either R1 or R2 represents a group represented by -L-D); as an active ingredient exhibits an excellent effect.

Abstract: An amide derivative represented by Formula (3), which exhibits excellent efficacy in pest control effect, is produced by allowing a compound represented by the following Formula (1) and a compound represented by Formula (2) to react with each other. In Formula (1) to Formula (3), Y1 and Y2 each represent a halogen atom or a haloalkyl group; Rf represents a C3-C4 perfluoroalkyl group; and R1 and R2 each represent a hydrogen atom or an alkyl group; LG represents a leaving group; T represents a hydrogen atom or a fluorine atom; X1, X3, X4, and X5 each represent a hydrogen atom, a halogen atom, or the like; and A represents a nitrogen atom, a methine group, or the like.

Abstract: An amplifier circuit including a plurality of CMOS (Complementary Metal Oxide Semiconductor) inverter circuits connected in parallel with each other. The CMOS inverter circuits each include a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, gates of the first PMOS and NMOS transistors, a second PMOS transistor, a first switch connected to a gate of the second PMOS transistor, a second NMOS transistor, and a second switch connected to a gate of the second NMOS transistor.

Abstract: Disclosed herein is a subtractor circuit for outputting an output voltage as a difference between a first input voltage and a second input voltage. The subtractor circuit may include a first semiconductor element, a second semiconductor element, a third semiconductor element, a fourth semiconductor element, a fifth semiconductor element, and a sixth semiconductor element configured to each invert a voltage input to an input terminal and output the inverted voltage from an output terminal; an input terminal of the first semiconductor element; an input terminal of the second semiconductor element; an output terminal of the first semiconductor element; and an output terminal of the third semiconductor element.

Abstract: A signal amplifier includes a discrete-variable-gain amplifying unit, a gain of which takes a discrete value and changes stepwise, a linear-variable-gain amplifying unit connected in series to the discrete-variable-gain amplifying unit, a gain of which changes continuously, control-signal outputting means for detecting a level of an output signal from a series connection circuit of the discrete-variable-gain amplifying unit and the linear-variable-gain amplifying unit and outputting a control signal corresponding to a difference between the level of the output signal and a reference voltage set as a comparative level to control the gain of the linear-variable-gain amplifying unit, and gain-switching control means for controlling to switch the gain of the discrete-variable-gain amplifying unit when the control signal deviates from a setting range for the control signal that is set according to a variable gain range of the discrete-variable-gain amplifying unit.

Abstract: Since centers of a second gear, a fourth gear and a sixth gear coincide with each other and are disposed rotatably round a circumference of the same long shaft, a compact configuration can be realized while using a gear train of five gears to obtain a reduction gear ratio of a high gear ratio. The configuration in which the three gears have the same rotational center shaft in the way described above in an actuator which incorporates a plurality of gears is advantageous in that the number of center shafts is reduced and that the number of supporting holes in a housing which support center shafts is reduced.

Abstract: An impedance conversion circuit including: a first voltage-to-current converter and a second voltage-to-current converter supplied with differential input signal voltages; an inverting amplifier; and a third voltage-to-current converter for feedback; wherein a first resistance and a second resistance are connected in series with each other between an input terminal and an output terminal of the inverting amplifier, an output terminal of the first voltage-to-current converter is connected to the input terminal of the inverting amplifier, an output terminal of the second voltage-to-current converter is connected to a connection node of the first resistance and the second resistance, the output terminal of the inverting amplifier is connected to an input terminal of the third voltage-to-current converter, an output terminal of the third voltage-to-current converter is connected to an input terminal of the first voltage-to-current converter, and an impedance is connected between the connection node and a ground.

Abstract: An amplifier circuit including a plurality of CMOS (Complementary Metal Oxide Semiconductor) inverter circuits connected in parallel with each other. The CMOS inverter circuits each include a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, gates of the first PMOS and NMOS transistors, a second PMOS transistor, a first switch connected to a gate of the second PMOS transistor, a second NMOS transistor, and a second switch connected to a gate of the second NMOS transistor.

Abstract: Disclosed herein is a subtractor circuit for outputting an output voltage as a difference between a first input voltage and a second input voltage. The subtractor circuit may include a first semiconductor element, a second semiconductor element, a third semiconductor element, a fourth semiconductor element, a fifth semiconductor element, and a sixth semiconductor element configured to each invert a voltage input to an input terminal and output the inverted voltage from an output terminal; an input terminal of the first semiconductor element; an input terminal of the second semiconductor element; an output terminal of the first semiconductor element; and an output terminal of the third semiconductor element.

Abstract: A conventional multiplier which uses a MOS transistor has a subject that, in order to compensate for a variation of a bias voltage or the like, it is necessary to add a complicated correcting circuit to an outputting section or the like, and the circuit scale becomes great and the power consumption increases. A multiplier includes NMOS transistors (3, 4, 5) and constant voltage sources (6, 9, 12) connected to the gates of the NMOS transistors (3, 4, 5), respectively, and the voltage value of a constant voltage source (9) and the voltage value of another constant voltage source (12) are set equal to each other. Further, the NMOS transistor (4) and the NMOS transistor (5) are formed same as each other.

Abstract: An impedance conversion circuit including: a first voltage-to-current converter and a second voltage-to-current converter supplied with differential input signal voltages; an inverting amplifier; and a third voltage-to-current converter for feedback; wherein a first resistance and a second resistance are connected in series with each other between an input terminal and an output terminal of the inverting amplifier, an output terminal of the first voltage-to-current converter is connected to the input terminal of the inverting amplifier, an output terminal of the second voltage-to-current converter is connected to a connection node of the first resistance and the second resistance, the output terminal of the inverting amplifier is connected to an input terminal of the third voltage-to-current converter, an output terminal of the third voltage-to-current converter is connected to an input terminal of the first voltage-to-current converter, and an impedance is connected between the connection node and a ground.

Abstract: A signal amplifier includes a discrete-variable-gain amplifying unit, a gain of which takes a discrete value and changes stepwise, a linear-variable-gain amplifying unit connected in series to the discrete-variable-gain amplifying unit, a gain of which changes continuously, control-signal outputting means for detecting a level of an output signal from a series connection circuit of the discrete-variable-gain amplifying unit and the linear-variable-gain amplifying unit and outputting a control signal corresponding to a difference between the level of the output signal and a reference voltage set as a comparative level to control the gain of the linear-variable-gain amplifying unit, and gain-switching control means for controlling to switch the gain of the discrete-variable-gain amplifying unit when the control signal deviates from a setting range for the control signal that is set according to a variable gain range of the discrete-variable-gain amplifying unit.

Abstract: An impedance conversion circuit including: a first voltage-to-current converter and a second voltage-to-current converter supplied with differential input signal voltages; an inverting amplifier; and a third voltage-to-current converter for feedback; wherein a first resistance and a second resistance are connected in series with each other between an input terminal and an output terminal of the inverting amplifier, an output terminal of the first voltage-to-current converter is connected to the input terminal of the inverting amplifier, an output terminal of the second voltage-to-current converter is connected to a connection node of the first resistance and the second resistance, the output terminal of the inverting amplifier is connected to an input terminal of the third voltage-to-current converter, an output terminal of the third voltage-to-current converter is connected to an input terminal of the first voltage-to-current converter, and an impedance is connected between the connection node and a ground.

Abstract: An impedance conversion circuit including: a first voltage-to-current converter and a second voltage-to-current converter supplied with differential input signal voltages; an inverting amplifier; and a third voltage-to-current converter for feedback; wherein a first resistance and a second resistance are connected in series with each other between an input terminal and an output terminal of the inverting amplifier, an output terminal of the first voltage-to-current converter is connected to the input terminal of the inverting amplifier, an output terminal of the second voltage-to-current converter is connected to a connection node of the first resistance and the second resistance, the output terminal of the inverting amplifier is connected to an input terminal of the third voltage-to-current converter, an output terminal of the third voltage-to-current converter is connected to an input terminal of the first voltage-to-current converter, and an impedance is connected between the connection node and a ground.

Abstract: An amplifier circuit includes a CMOS inverter circuit that eliminates a DC offset caused by variations in characteristics of elements in each manufacturing process and is thus applicable to analog signal processing. The CMOS inverter circuit includes a PMOS transistor, a first NMOS transistor, a second NMOS transistor connected to the first NMOS transistor to increase a source voltage of the first NMOS transistor, and DC offset detecting means for detecting a DC offset and for applying a voltage adjusted so as to reduce the DC offset to a gate of the second NMOS transistor.

Abstract: A conventional multiplier which uses a MOS transistor has a subject that, in order to compensate for a variation of a bias voltage or the like, it is necessary to add a complicated correcting circuit to an outputting section or the like, and the circuit scale becomes great and the power consumption increases. A multiplier includes NMOS transistors (3, 4, 5) and constant voltage sources (6, 9, 12) connected to the gates of the NMOS transistors (3, 4, 5), respectively, and the voltage value of a constant voltage source (9) and the voltage value of another constant voltage source (12) are set equal to each other. Further, the NMOS transistor (4) and the NMOS transistor (5) are formed same as each other.

Abstract: An amplifier circuit including a CMOS inverter circuit that eliminates a DC offset caused by variations in characteristics of elements in each manufacturing process and is thus applicable to analog signal processing. The CMOS inverter circuit including a PMOS transistor (11), an NMOS transistor (12), and the like is provided with an NMOS transistor (13) connected to the NMOS transistor (12) to increase a source voltage of the NMOS transistor (12) and DC offset detecting means for detecting a DC offset and applying a voltage adjusted so as to reduce the DC offset to a gate of the NMOS transistor (13).

Abstract: A voltage/current converter circuit includes a first differential pair circuit containing a first pair of MOS transistors, a second differential pair circuit containing a second pair of MOS transistors wherein the drain terminals thereof are connected to each of the source terminals of the first MOS transistor differential pair circuit, and a resistor element connected between the sources of the second MOS transistor differential pair circuit, wherein the gates of the second pair of MOS transistors are mutually connected to the drains of the MOS transistors of the other side, and the sources of the two MOS transistors are each grounded via an electric current source. Thus, a high-gain amplifier with improved linearity is realized with a small number of elements, thereby reducing electric power consumption and reduced IC chip surface area.