Patents by Inventor Atsushi Horie

Atsushi Horie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080290956
    Abstract: A surface-mount type crystal oscillator includes a container body having a recess and made up of laminated ceramic, a crystal blank accommodated in the container body, and an IC chip made up of a semiconductor substrate in which at least an oscillation circuit using the crystal blank is formed. The IC chip is electrically and mechanically connected to an inner bottom surface of the recess so that a circuit formation surface thereof faces the inner bottom surface. The IC chip has a first electrode formed on a surface thereof which is opposite the inner bottom surface, and a second electrode is formed on a surface which is disposed in the recess, the first and second electrodes being connected together by wire bonding. Alternatively, an outer peripheral side surface of the IC chip is thermally coupled to an inner peripheral surface of the recess by a conductive adhesive.
    Type: Application
    Filed: May 21, 2008
    Publication date: November 27, 2008
    Applicant: NIHON DEMPA KOGYO CO., LTD.
    Inventor: Atsushi HORIE
  • Patent number: 5634061
    Abstract: Disclosed is a programmable logic array (PLA), comprising an AND plane comprising a plurality of input lines and a plurality of product term lines crossing the input lines, an OR plane comprising the product term lines and a plurality of output lines crossing the product term lines, a power source VDD providing an electrical power to the AND and OR planes, and control line for controlling the supply of the electric power to the AND and OR planes, wherein the electrical power from the power source VDD is provided to the PLA when a signal indicating the use of the PLA is provided to the control line, and the supply of the electrical power from the power source VDD to the PLA is stopped on receipt of a signal designating that the PLA is in the unused state. In addition, various data processing systems incorporating the PLA are disclosed.
    Type: Grant
    Filed: April 25, 1994
    Date of Patent: May 27, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Horie, Tohru Utsumi
  • Patent number: 5083047
    Abstract: Disclosed is a precharged-type logic circuit comprising dummy precharge lines connected to a load capacitance that is equivalent to the maximum or still larger as compared with load capacitances of respective precharge lines, wherein a precharge completion time of the dummy precharge lines is detected as a precharge completion time of the precharge lines, so that the precharge operation of the precharge lines is stopped under state of the dummy precharge line.
    Type: Grant
    Filed: October 22, 1990
    Date of Patent: January 21, 1992
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Horie, Kimiyoshi Usami